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1. 发明授权

US06720604B1 Capacitor for an integrated circuit 有权
标题翻译：集成电路电容器
公开(公告)号：US06720604B1
公开(公告)日：2004-04-13
申请号：US09250500
申请日：1999-02-16
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2994
CPC分类号： H01L28/75 , H01L21/28568 , H01L27/1085 , H01L28/60
摘要： The present invention provides a capacitor comprising a conductive plug comprising a top surface and exposed sidewalls, wherein the sidewalls comprise a layer selected from the group consisting of titanium and titanium nitride, and an electrode material layer over the conductive plug sidewalls, wherein the layer of electrode material is not titanium nor titanium nitride.
摘要翻译：本发明提供了一种电容器，其包括导电插塞，其包括顶表面和暴露的侧壁，其中所述侧壁包括选自钛和氮化钛的层，以及在导电插塞侧壁上的电极材料层，其中，电极材料不是钛和氮化钛。

2. 发明授权

US06458016B2 Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method 有权
标题翻译：抛光液，抛光法，半导体器件及半导体器件的制造方法
公开(公告)号：US06458016B2
公开(公告)日：2002-10-01
申请号：US09894116
申请日：2001-06-28
申请人： Sailesh Mansinh Merchant , Sudhanshu Misra , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sailesh Mansinh Merchant , Sudhanshu Misra , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： B24B2118
CPC分类号： B24B37/005 , B24B37/044 , C09G1/02
摘要： A polishing fluid comprising a distributed organic phase and a continuous aqueous phase. The distributed phase has at least one complexing agent and the aqueous phase has abrasive particles dispersed therein. Reaction products generated during polishing interact with the complexing agent(s) to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.
摘要翻译：包括分布有机相和连续水相的抛光液。分布相具有至少一种络合剂，水相中分散有磨料颗粒。在抛光过程中产生的反应产物与络合剂相互作用形成有机金属络合物。进一步公开了一种利用抛光液的抛光方法，半导体器件和半导体器件制造方法。

3. 发明授权

US06439972B2 Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method 有权
标题翻译：抛光液，抛光法，半导体器件及半导体器件的制造方法
公开(公告)号：US06439972B2
公开(公告)日：2002-08-27
申请号：US09894117
申请日：2001-06-28
申请人： Sudhanshu Misra , Pradip Kumar Roy , Sundar Srinivasaan Chetlur , Vivek Saxena
发明人： Sudhanshu Misra , Pradip Kumar Roy , Sundar Srinivasaan Chetlur , Vivek Saxena
IPC分类号： B24B2118
CPC分类号： B24B37/044 , C09G1/02
摘要： A polishing fluid comprising a distributed organic phase and a continuous aqueous phase, each phase comprising at least one complexing agent. The aqueous phase also having abrasive particles dispersed therein. Reaction products generated during polishing interact with the aqueous phase complexing agent to form water soluble metallic complexes, the water soluble metallic complexes diffuse to an organic/water interface where they release complexing agent molecules in the aqueous phase and generate metal ions which interact with the organic phase complexing agent to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.
摘要翻译：一种包含分布有机相和连续水相的抛光液，每相包含至少一种络合剂。水相中也分散有磨粒。在抛光过程中产生的反应产物与水相络合剂相互作用以形成水溶性金属络合物，水溶性金属络合物扩散到有机/水界面，在那里它们释放水相中的络合剂分子并产生与有机物相互作用的金属离子相络合剂形成有机金属络合物。进一步公开了一种利用抛光液的抛光方法，半导体器件和半导体器件制造方法。

4. 发明授权

US06387772B1 Method for forming trench capacitors in SOI substrates 有权
标题翻译：在SOI衬底中形成沟槽电容器的方法
公开(公告)号：US06387772B1
公开(公告)日：2002-05-14
申请号：US09557536
申请日：2000-04-25
申请人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
发明人： Sailesh Chittipeddi , Charles Walter Pearce , Pradip Kumar Roy
IPC分类号： H01L2120
CPC分类号： H01L29/66181 , H01L27/1203 , H01L29/945
摘要： A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.
摘要翻译：形成在SOI衬底上的沟槽电容器延伸穿过上硅层和绝缘层并进入半导体基底衬底。沟槽电容器的外部电极包括半导体基底基板的限定形成沟槽电容器的沟槽的部分。外电极耦合到紧邻沟槽电容器形成的接触结构，并延伸穿过绝缘层。用于同时制造沟槽电容器和接触结构的方法包括形成两个沟槽开口，在一个沟槽开口上形成电介质衬垫，然后用半导体材料填充每个沟槽开口。

5. 发明授权

US06368200B1 Polishing pads from closed-cell elastomer foam 有权
标题翻译：来自闭孔弹性体泡沫的抛光垫
公开(公告)号：US06368200B1
公开(公告)日：2002-04-09
申请号：US09516836
申请日：2000-03-02
申请人： Sailesh Mansinh Merchant , Sudhanshu Misra , Pradip Kumar Roy
发明人： Sailesh Mansinh Merchant , Sudhanshu Misra , Pradip Kumar Roy
IPC分类号： B24D1100
CPC分类号： B24B37/24
摘要： A polishing pad formed from closed-cell elastomer foam includes a population of bubbles within the pad. As the pad wears due to polishing and the polishing surface recedes, the freshly formed polishing surface includes pores formed of the newly exposed bubbles. The pores receive and retain polishing slurry and aid in the chemical mechanical polishing process. Pad conditioning is not required because new pores are constantly being created at the pad surface as the surface recedes during polishing. The method for forming the polishing pad includes the injection of gas bubbles into the viscous elastomer material used to form the pad. Process conditions are chosen to maintain gas bubbles within the elastomer material during the curing and solidifying process steps.
摘要翻译：由闭孔弹性体泡沫形成的抛光垫包括垫内的气泡群。当由于抛光而抛光垫磨损并且抛光表面后退时，新形成的抛光表面包括由新露出的气泡形成的孔。孔隙接收和保留抛光浆料并有助于化学机械抛光过程。不需要衬垫调节，因为在抛光期间表面后退时，在衬垫表面上不断产生新的孔。用于形成抛光垫的方法包括将气泡注入用于形成垫的粘性弹性体材料中。选择工艺条件以在固化和固化过程步骤期间保持弹性体材料内的气泡。

6. 发明授权

US06339246B1 Tungsten silicide nitride as an electrode for tantalum pentoxide devices 有权
标题翻译：硅化钨氮化物作为五氧化二钽器件的电极
公开(公告)号：US06339246B1
公开(公告)日：2002-01-15
申请号：US09209787
申请日：1998-12-11
申请人： Isik C. Kizilyalli , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Isik C. Kizilyalli , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , C23C14/0641 , C23C14/0682 , H01L21/28088 , H01L21/28097 , H01L29/4975 , H01L29/517
摘要： The specification describes a process for making gate electrodes for silicon MOS transistor devices having tantalum pentoxide gate dielectrics. The gate electrode includes a layer of tungsten silicide, and, preferably a layer of tungsten suicide nitride. The tungsten silicide nitride/tungsten silicide reduces oxygen depletion effects in the tantalum pentoxide. The layers are preferably formed in situ in a PVD apparatus.
摘要翻译：该说明书描述了制造具有五氧化钼栅极电介质的硅MOS晶体管器件的栅电极的工艺。栅电极包括一层硅化钨，优选一层硅化钨。硅化钨氮化硅/硅化钨减少五氧化二钽中的氧耗尽作用。这些层优选在PVD装置中原位形成。

7. 发明授权

US06320238B1 Gate structure for integrated circuit fabrication 有权
标题翻译：集成电路制造的门结构
公开(公告)号：US06320238B1
公开(公告)日：2001-11-20
申请号：US09339895
申请日：1999-06-25
申请人： Isik C. Kizilyalli , Yi Ma , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Isik C. Kizilyalli , Yi Ma , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
摘要翻译：本发明涉及一种具有设置在其上设置有栅电极的基板上的电介质材料层的栅极堆叠结构。在一个示例性实施例中，电介质材料层具有2.2nm或更小的等效电气厚度，并且包括除二氧化硅之外的至少一个层。此外，本发明的电介质材料层能够进行器件定标，并且与常规栅极电介质相比提供（1）降低的漏电流和改善的隧穿电压; 和（2）当专门用作栅极电介质时，避免超薄二氧化硅的危险。

8. 发明授权

US06306780B1 Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation 有权
标题翻译：制造具有增加的起泡，剥离，提升或网状抗性的光致抗蚀剂层的方法
公开(公告)号：US06306780B1
公开(公告)日：2001-10-23
申请号：US09698375
申请日：2000-10-26
申请人： Konstantin K. Bourdelle , Pradip Kumar Roy
发明人： Konstantin K. Bourdelle , Pradip Kumar Roy
IPC分类号： H01L21324
CPC分类号： G03F7/40 , H01L21/266
摘要： A method for making a photoresist layer includes forming a photoresist layer adjacent a substrate and patterning the photoresist layer. The photoresist layer may include at least one of a solvent and water. The photoresist layer may then be heated and exposed to ultraviolet light during the heating to reduce at least one of the solvent and water therein. As a result, the formation of gases in the photoresist layer during ion implantation is reduced, which thus reduces damage to the photoresist layer from blistering, peeling, lifting, or reticulation, for example. The photoresist layer may be formed to have a thickness greater than about 2 &mgr;m, for example, to block high-current, high-dosage, high-energy ion implantation. Exposing may include exposing the photoresist layer to ultraviolet light having a power density in a range of about 200 to 500 mW/cm2, and, more preferably, about 270 to 360 mW/cm2, and having a wavelength in a range of about 200 to 300 nm, for example. The photoresist layer may be heated for about 200 to 400 seconds and to a temperature in a range of about 150° C. to 250° C., and more preferably about 230° C. to 250° C. Furthermore, heating may include maintaining the photoresist layer at a high temperature for about 15 to 60 seconds.
摘要翻译：制造光致抗蚀剂层的方法包括在衬底附近形成光致抗蚀剂层并图案化光致抗蚀剂层。光致抗蚀剂层可以包括溶剂和水中的至少一种。然后可以在加热期间将光致抗蚀剂层加热并暴露于紫外光以减少其中的至少一种溶剂和水。结果，在离子注入期间光致抗蚀剂层中的气体的形成被减少，从而减少例如由起泡，剥离，提升或网状构成的光致抗蚀剂层的损伤。光致抗蚀剂层可以形成为具有大于约2μm的厚度，例如阻挡高电流，高剂量，高能离子注入。曝光可以包括将光致抗蚀剂层暴露于功率密度在约200至500mW / cm 2的范围内，更优选约270至360mW / cm 2的范围内的波长在约200至 300nm。光致抗蚀剂层可以加热约200至400秒，并且可以在约150℃至250℃，更优选约230℃至250℃的温度范围内加热。此外，加热可包括维持光致抗蚀剂层在高温下约15至60秒。

9. 发明授权

US06281110B1 Method for making an integrated circuit including deutrium annealing of metal interconnect layers 有权
标题翻译：制造包括金属互连层的中和退火的集成电路的方法
公开(公告)号：US06281110B1
公开(公告)日：2001-08-28
申请号：US09361733
申请日：1999-07-27
申请人： Isik C. Kizilyalli , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Isik C. Kizilyalli , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L214763
CPC分类号： H01L21/321 , H01L21/76838 , H01L21/76877
摘要： A method of making an integrated circuit includes forming a plurality of copper interconnect layers adjacent a semiconductor substrate. The plurality of copper interconnect layers are then annealed, in a deuterium ambient, prior to chemical mechanical polishing of such layers. The microstructure of each of the copper interconnect layers is thereby stabilized.
摘要翻译：制造集成电路的方法包括在半导体衬底附近形成多个铜互连层。然后，在这些层的化学机械抛光之前，多个铜互连层在氘环境中退火。每个铜互连层的微观结构由此稳定。

10. 发明授权

US06249016B1 Integrated circuit capacitor including tapered plug 有权
标题翻译：集成电路电容器包括锥形插头
公开(公告)号：US06249016B1
公开(公告)日：2001-06-19
申请号：US09364603
申请日：1999-07-30
申请人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
发明人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/40
摘要： An integrated circuit capacitor includes a first dielectric layer adjacent a substrate and having a trench therein, and a metal plug comprising an upper portion extending upwardly into the trench, and a lower portion disposed in the first dielectric layer. The lower portion has a tapered width which increases in a direction toward the substrate to thereby secure the metal plug in the dielectric layer. Preferably, the upper portion is also tapered. Furthermore, a second dielectric layer is adjacent the metal plug with an upper electrode thereon.
摘要翻译：集成电路电容器包括与衬底相邻并且在其中具有沟槽的第一电介质层和包括向上延伸到沟槽中的上部的金属插塞和设置在第一电介质层中的下部。下部具有朝向基板的方向增加的锥形宽度，从而将金属塞固定在电介质层中。优选地，上部也是锥形的。此外，第二电介质层与其上的上电极邻近金属插塞。

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