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1. 发明授权

US06727588B1 Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 有权
标题翻译：集成电路金属间介质中的防扩散阻挡层
公开(公告)号：US06727588B1
公开(公告)日：2004-04-27
申请号：US09377386
申请日：1999-08-19
申请人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
发明人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/76829 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.
摘要翻译：可以防止杂质在低介电常数材料中迁移的帽或阻挡层，从而防止杂质在多级集成电路结构的后续级别中侵袭导电元件。集成电路可以通过在集成电路的上层设置第一介电层和导电层之间设置防扩散阻挡层来制造。扩散防止阻挡层可以在含杂质的电介质材料上的原位形成，随后在其上布置金属层，并且进一步处理多层电介质结构以包括抛光。帽或阻挡层的原位沉积防止了含杂质层暴露于大气中，从而避免了由吸湿，吸氢等引起的层的污染。在示例性实施例中，防扩散阻挡层是含有氧化硅或富硅氧化硅SiO x的材料，其中x优选小于2。

2. 发明授权

US06274933B1 Integrated circuit device having a planar interlevel dielectric layer 有权
标题翻译：具有平面层间电介质层的集成电路器件
公开(公告)号：US06274933B1
公开(公告)日：2001-08-14
申请号：US09376233
申请日：1999-08-17
申请人： Mahjoub Ali Abdelgadir , Alvaro Maury
发明人： Mahjoub Ali Abdelgadir , Alvaro Maury
IPC分类号： H01L2548
CPC分类号： H01L21/28194 , C23C14/083 , C23C14/5806 , C23C14/5873 , H01L21/31612 , H01L21/31629 , H01L21/76801 , H01L21/76819 , H01L21/76834 , H01L21/76837 , H01L21/76888 , H01L23/5222 , H01L23/5223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L28/60 , H01L29/51 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a conductive layer adjacent a semiconductor substrate. The conductive layer includes conductive lines having gaps therebetween. A fluoro-silicate glass (FSG) layer is over the patterned conductive layer fills the gaps between conductive lines. Also, an undoped oxide layer is on the FSG layer. Peaks of the FSG layer which overlie the conductive metal lines have been reduced by CMP. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.
摘要翻译：集成电路包括邻近半导体衬底的导电层。导电层包括其间具有间隙的导电线。氟化硅玻璃（FSG）层在图案化的导电层之上，并填充导电线之间的间隙。此外，未掺杂的氧化物层在FSG层上。覆盖导电金属线的FSG层的峰已通过CMP降低。因此，后续导电层基本上被保护免受来自FSG层的氟的暴露。

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