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1. 发明授权

US06555425B2 Method for manufacturing transistor 有权
公开(公告)号：US06555425B2
公开(公告)日：2003-04-29
申请号：US09880519
申请日：2001-06-12
申请人： Kuo-Tai Huang , Ellen Cheng
发明人： Kuo-Tai Huang , Ellen Cheng
IPC分类号： H01L218238
CPC分类号： H01L29/66583 , H01L21/28114 , H01L29/41783 , H01L29/42376 , H01L29/6656 , H01L29/7834
摘要： A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.

2. 发明授权

US08148249B2 Methods of fabricating high-k metal gate devices 有权
标题翻译：制造高k金属栅极器件的方法
公开(公告)号：US08148249B2
公开(公告)日：2012-04-03
申请号：US12405965
申请日：2009-03-17
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin , Yu-Chao Lin
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin , Yu-Chao Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/823828 , H01L21/3221 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
摘要翻译：公开了制造具有高k /金属栅极特征的半导体器件的方法。在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

3. 发明授权

US07811892B2 Multi-step annealing process 有权
标题翻译：多步退火工艺
公开(公告)号：US07811892B2
公开(公告)日：2010-10-12
申请号：US11308508
申请日：2006-03-31
申请人： Yun-Ren Wang , Ying-Wei Yen , Chien-Hua Lung , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Chien-Hua Lung , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L21/477
CPC分类号： H01L21/02337 , H01L21/02318 , H01L21/02329 , H01L21/0234 , H01L21/324 , H01L21/823462 , H01L29/66537 , H01L29/78
摘要： A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.
摘要翻译：描述制造介电层的方法。提供衬底，并且在衬底上形成电介质层。介电层通过氮化处理进行。介电层通过第一退火工艺进行。在第一退火工艺中使用的第一种气体包括惰性气体和氧气。第一气体具有惰性气体与氧的第一分压比。介电层通过第二退火工艺进行。在第二退火中使用的第二气体包括惰性气体和氧气。第二气体具有惰性气体与氧气的第二分压比，第二分压比小于第一分压比。两个退火工艺的至少一个退火温度等于或大于950℃。本发明改善了分布在介电层中的氮掺杂剂的均匀性。

4. 发明授权

US07709316B2 Method of fabricating gate structure 有权
标题翻译：栅极结构的制作方法
公开(公告)号：US07709316B2
公开(公告)日：2010-05-04
申请号：US12192128
申请日：2008-08-15
申请人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L21/8249
CPC分类号： H01L21/28202 , H01L21/28088 , H01L21/76822 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.
摘要翻译：提供一种制造栅极结构的方法。首先，在基板上形成牺牲氧化物层。进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子。接下来，除去牺牲氧化物层。进行再氧化处理以在衬底的表面上产生界面层。在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

5. 发明申请

US20100038721A1 METHOD OF FORMING A SINGLE METAL THAT PERFORMS N WORK FUNCTION AND P WORK FUNCTION IN A HIGH-K/METAL GATE PROCESS 有权
标题翻译：在高K /金属浇口工艺中形成单一金属的方法，其具有N个工作功能和P功能
公开(公告)号：US20100038721A1
公开(公告)日：2010-02-18
申请号：US12492889
申请日：2009-06-26
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Donald Y. Chao , Yi-Shien Mor , Kuo-Tai Huang
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Donald Y. Chao , Yi-Shien Mor , Kuo-Tai Huang
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/28194 , H01L21/823842 , H01L29/4966 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在半导体衬底上形成栅极电介质，在栅极电介质之上或之下形成覆盖层，在覆盖层上形成金属层，金属层具有第一功函数，处理金属层的一部分，使得所述金属层的所述部分的功函数从所述第一功函数变为第二功函数，并且从具有所述第一功函数的所述金属层的未处理部分形成第一金属栅极，并且从所述处理的所述金属栅极形成第二金属栅极具有第二功函数的金属层的部分。

6. 发明授权

US07553763B2 Salicide process utilizing a cluster ion implantation process 有权
标题翻译：利用簇离子注入工艺的自杀过程
公开(公告)号：US07553763B2
公开(公告)日：2009-06-30
申请号：US11463012
申请日：2006-08-08
申请人： Tsai-Fu Hsiao , Chin-Cheng Chien , Kuo-Tai Huang
发明人： Tsai-Fu Hsiao , Chin-Cheng Chien , Kuo-Tai Huang
IPC分类号： H01L21/20
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28052 , H01L29/665 , H01L29/6656
摘要： A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.
摘要翻译：自对准硅化物工艺包括提供包括至少预定的自对准硅化物区域的硅衬底，进行聚簇离子注入工艺以在硅衬底的预定自对准硅化物区域中形成非晶化层，在非晶化层的表面上形成金属层并使金属层与非晶化层反应，以在硅衬底的表面上形成硅化物层。

7. 发明申请

US20070102774A1 GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：门结构及其制作方法
公开(公告)号：US20070102774A1
公开(公告)日：2007-05-10
申请号：US11164025
申请日：2005-11-08
申请人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/28202 , H01L21/28088 , H01L21/76822 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.
摘要翻译：提供一种制造栅极结构的方法。首先，在基板上形成牺牲氧化物层。进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子，并产生浓度分布，使得氮的浓度逐渐增加，然后在牺牲氧化物层中具有氮的最大浓度朝向衬底减小。接下来，除去牺牲氧化物层。进行再氧化处理以在衬底的表面上产生界面层。在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

8. 发明授权

US06555485B1 Method for fabricating a gate dielectric layer 有权
标题翻译：栅极电介质层的制造方法
公开(公告)号：US06555485B1
公开(公告)日：2003-04-29
申请号：US10055891
申请日：2002-01-28
申请人： Chuan-Hsi Liu , Hsiu-Shan Lin , Yu-Yin Lin , Tung-Ming Pan , Kuo-Tai Huang
发明人： Chuan-Hsi Liu , Hsiu-Shan Lin , Yu-Yin Lin , Tung-Ming Pan , Kuo-Tai Huang
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/51 , H01L29/518
摘要： This invention relates to a method for forming a gate dielectric layer, and, more particularly, to a method for treating a base oxide layer by using a remote plasma nitridation procedure and a thermal annealing treatment in turn to form the gate dielectric layer. The first step of the present invention is to form a base oxide layer on a substrate of a wafer. The base oxide layer can be formed using any kind of method. Then nitrogen ions are introduced into the base oxide layer using the remote plasma nitridation procedure to form a remote plasma nitrided oxide layer. Finally, the wafer is placed in a reaction chamber which comprises oxygen (O2) or nitric monoxide (NO) to treat the remote plasma nitrided oxide layer using the thermal annealing procedure and the gate dielectric layer of the present invention is formed.
摘要翻译：本发明涉及一种用于形成栅极电介质层的方法，更具体地，涉及一种通过使用远程等离子体氮化处理和热退火处理依次形成栅极介电层来处理基底氧化物层的方法。本发明的第一步是在晶片的基片上形成基底氧化物层。基底氧化物层可以使用任何种类的方法形成。然后使用远程等离子体氮化方法将氮离子引入基底氧化物层中以形成远程等离子体氮化氧化物层。最后，将晶片放置在包含氧（O 2）或一氧化氮（NO）的反应室中，以使用热退火程序处理远程等离子体氮化氧化物层，并形成本发明的栅介质层。

9. 发明授权

US06368923B1 Method of fabricating a dual metal gate having two different gate dielectric layers 有权
标题翻译：制造具有两个不同栅极电介质层的双金属栅极的方法
公开(公告)号：US06368923B1
公开(公告)日：2002-04-09
申请号：US09561577
申请日：2000-04-28
申请人： Kuo-Tai Huang
发明人： Kuo-Tai Huang
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , H01L21/82345
摘要： A method of fabricating a dual metal gate. A cell region and a peripheral region are formed on a substrate, and a first dummy gate electrode and a second dummy gate electrode are formed on the substrate, respectively, in the cell region and in the peripheral region. A patterned first dielectric layer is formed above the substrate, and the layer exposes the surfaces of the first dummy gate electrode and the second dummy gate electrode. The first dummy gate electrode and the second dummy gate electrode are then removed to expose the substrate, and an oxide layer is formed on the exposed substrate in the peripheral region. A remote plasma nitridation step is performed to nitridate the surface of the exposed substrate in the cell region and to nitridate the oxide layer into a material layer in the peripheral region. A second dielectric layer and a conducting layer are formed sequentially above the substrate. The conducting layer fills up the trenches that are formed by removing the first dummy gate electrode and the second dummy gate electrode. A part of the second dielectric layer and a part of the conducting layer are removed until the surface of the first dielectric layer is exposed, and a dual metal gate is completed thereon.
摘要翻译：一种制造双金属栅极的方法。在基板上形成单元区域和周边区域，并且在单元区域和周边区域中分别在基板上形成第一伪栅极电极和第二伪栅极电极。在衬底上形成图案化的第一电介质层，并且该层露出第一虚拟栅极电极和第二虚拟栅电极的表面。然后去除第一伪栅极电极和第二虚拟栅极电极以露出衬底，并且在外围区域中的暴露的衬底上形成氧化物层。进行远程等离子体氮化步骤以使细胞区域中暴露的基底的表面氮化，并将氧化物层氮化为外围区域中的材料层。在衬底上顺序地形成第二电介质层和导电层。导电层填充通过去除第一伪栅极电极和第二虚拟栅极电极而形成的沟槽。去除第二电介质层的一部分和导电层的一部分直到第一介电层的表面露出，并且在其上完成双金属栅极。

10. 发明授权

US6037206A Method of fabricating a capacitor of a dynamic random access memory 失效
标题翻译：制造动态随机存取存储器的电容器的方法
公开(公告)号：US6037206A
公开(公告)日：2000-03-14
申请号：US080116
申请日：1998-05-15
申请人： Kuo-Tai Huang , Hsi-Ta Chuang , Tri-Rung Yew
发明人： Kuo-Tai Huang , Hsi-Ta Chuang , Tri-Rung Yew
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for fabricating a capacitor of a DRAM includes a lower conductive layer of the capacitor is formed over a substrate and is electrically coupled to an interchangeable source/drain region through a contact window penetrating an insulating layer. Then performing etching process on the lower conductive layer so as to form a fence-like plate with a higher height than a thickness of the lower conductive layer and adhere to the lower conductive layer. Next a media conductive layer is formed over the lower conductive layer and the fence-like plate. Then the technology of etching back is utilized to round the sharp area on the tip of the fence-like plate. The lower conductive layer and the media conductive layer are electrically coupled together as a lower electrode. Then, a dielectric thin film is formed over the media conductive layer and an upper electrode is formed over the dielectric thin film. Therefore, a MIM capacitor according to the preferred embodiment of the invention is formed.
摘要翻译：一种用于制造DRAM电容器的方法包括：电容器的下导电层形成在衬底上，并通过穿透绝缘层的接触窗电耦合到可互换的源/漏区。然后对下导电层进行蚀刻处理，以形成具有比下导电层的厚度高的高度的栅栏状的板，并粘附到下导电层。接下来，在下导电层和栅栏状板上形成介质导电层。然后，利用蚀刻技术来围绕栅栏状板的尖端上的尖锐区域。下导电层和介质导电层作为下电极电耦合在一起。然后，在介质导电层上形成电介质薄膜，在电介质薄膜上方形成上电极。因此，形成根据本发明的优选实施例的MIM电容器。

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