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1. 发明申请

US20060289953A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20060289953A1
公开(公告)日：2006-12-28
申请号：US11390288
申请日：2006-03-28
申请人： Kiwamu Sakuma , Yoshinori Tsuchiya , Masato Koyama
发明人： Kiwamu Sakuma , Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L29/94
CPC分类号： H01L29/4908 , H01L21/823842 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/785 , H01L29/78654
摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a first gate insulating film, a first gate electrode and first source/drain regions. The first gate insulating film is formed on the first semiconductor layer. The first gate electrode is formed on the first gate insulating film. The first gate electrode includes crystal grains of a first metal consisting of Ru, and a second metal selected from the group consisting of W, Ni, Mo, Rh, Pd, Re Ir, and Pt. The second metal is segregated at a grain boundary between the crystal grains of the first metal. The first source/drain regions are formed in the first semiconductor layer, across the first gate insulating film from each other in a gate length direction of the first gate insulating film.
摘要翻译：半导体器件包括第一导电类型的第一半导体层，第一栅极绝缘膜，第一栅极电极和第一源极/漏极区域。第一栅极绝缘膜形成在第一半导体层上。第一栅电极形成在第一栅极绝缘膜上。第一栅电极包括由Ru组成的第一金属的晶粒和选自W，Ni，Mo，Rh，Pd，Re Ir和Pt的第二金属。第二金属在第一金属的晶粒之间的晶界处分离。第一源极/漏极区域在第一栅极绝缘膜的栅极长度方向上在第一半导体层中跨越第一栅极绝缘膜彼此形成。

2. 发明授权

US08053300B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08053300B2
公开(公告)日：2011-11-08
申请号：US11841817
申请日：2007-08-20
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分的第一电介质面向第一金属栅电极。

3. 发明申请

US20100171184A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100171184A1
公开(公告)日：2010-07-08
申请号：US12654490
申请日：2009-12-22
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分的第一电介质面向第一金属栅电极。

4. 发明授权

US07745888B2 Method of making p-channel and n-channel MIS transistors using single film formation of TaC 有权
标题翻译：使用TaC单膜形成制造p沟道和n沟道MIS晶体管的方法
公开(公告)号：US07745888B2
公开(公告)日：2010-06-29
申请号：US12232078
申请日：2008-09-10
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
摘要翻译：半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

5. 发明授权

US07718521B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07718521B2
公开(公告)日：2010-05-18
申请号：US12133605
申请日：2008-06-05
申请人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
摘要翻译：公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。

6. 发明申请

US20100032765A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20100032765A1
公开(公告)日：2010-02-11
申请号：US12549298
申请日：2009-08-27
申请人： Yoshinori TSUCHIYA , Masato Koyama
发明人： Yoshinori TSUCHIYA , Masato Koyama
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L29/4958 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/76802 , H01L21/76877 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/4966 , H01L29/4975 , H01L29/665
摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

7. 发明申请

US20090263950A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090263950A1
公开(公告)日：2009-10-22
申请号：US12491984
申请日：2009-06-25
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×10 20 cm -3或更高至1×10 22 cm -3或更小的铝原子。

8. 发明申请

US20090166749A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090166749A1
公开(公告)日：2009-07-02
申请号：US12233055
申请日：2008-09-18
申请人： Reika ICHIHARA , Yoshinori Tsuchiya , Hiroki Tanaka , Masahiko Yoshiki , Masato Koyama
发明人： Reika ICHIHARA , Yoshinori Tsuchiya , Hiroki Tanaka , Masahiko Yoshiki , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and second gate insulators formed inside of the first and second trenches, a first metal layer formed inside of the first trench via the first gate insulator, a second metal layer formed in a thickness of 1 monolayer or more and 1.5 nm or less inside of the second trench via the second gate insulator, a third metal layer formed on the second metal layer and containing at least one of a simple substance, a nitride, a carbide and an oxide of at least one metal element of alkaline earth metal elements and group III elements, first and second source/drain regions formed on the n- and p-type regions.
摘要翻译：半导体器件包括分别形成在衬底上的n型和p型半导体区，形成在衬底上的层间绝缘体，并且具有形成为达到n型和p型区的第一和第二沟槽。还包括形成在第一和第二沟槽内的第一和第二栅极绝缘体，经由第一栅极绝缘体形成在第一沟槽内部的第一金属层，形成为厚度为1单层或更多和1.5nm的第二金属层或更少的内部经由所述第二栅极绝缘体，形成在所述第二金属层上并且包含至少一种碱土金属元素的单质，氮化物，碳化物和氧化物中的至少一种的第三金属层金属元素和III族元素，形成在n型和p型区上的第一和第二源/漏区。

9. 发明授权

US07429776B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07429776B2
公开(公告)日：2008-09-30
申请号：US11235246
申请日：2005-09-27
申请人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
摘要翻译：公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。

10. 发明申请

US20080211034A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080211034A1
公开(公告)日：2008-09-04
申请号：US11871570
申请日：2007-10-12
申请人： Yoshinori Tsuchiya , Masato Koyama
发明人： Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28097 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/7845
摘要： A semiconductor device includes: a substrate and a p-channel MIS transistor. The p-channel MIS transistor includes: an n-type semiconductor region formed in the substrate; p-type first source and drain regions formed at a distance from each other in the n-type semiconductor region; a first gate insulating film formed on the n-type semiconductor region between the first source region and the first drain region; and a first gate electrode formed on the first gate insulating film. The first gate electrode includes a first nickel silicide layer having a Ni/Si composition ratio of 1 or greater, and a silicide layer formed on the first nickel silicide layer. The silicide layer contains a metal having a larger absolute value of oxide formation energy than that of Si, and a composition ratio of the metal to Si is smaller than the Ni/Si composition ratio.
摘要翻译：半导体器件包括：衬底和p沟道MIS晶体管。 p沟道MIS晶体管包括：形成在衬底中的n型半导体区域; 在n型半导体区域中形成为彼此间隔一定距离的p型第一源极和漏极区域; 形成在所述第一源极区域和所述第一漏极区域之间的所述n型半导体区域上的第一栅极绝缘膜; 以及形成在第一栅极绝缘膜上的第一栅电极。第一栅电极包括Ni / Si组成比为1或更大的第一硅化镍层和形成在第一硅化镍层上的硅化物层。硅化物层含有氧化物形成能量绝对值高于Si的金属，金属与Si的组成比小于Ni / Si组成比。

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