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1. 发明授权

US06504207B1 Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same 失效
标题翻译：创建集成了高性能逻辑和NVRAM的EEPROM存储器结构的方法，以及与之相同的操作条件
公开(公告)号：US06504207B1
公开(公告)日：2003-01-07
申请号：US09609292
申请日：2000-06-30
申请人： Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
发明人： Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , G11C16/0408 , H01L29/42328
摘要： A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.
摘要翻译：与高性能逻辑或NVRAM集成的EEPROM存储器件的方法和结构。 EEPROM器件包括浮置栅极和彼此自对准的程序栅极。在编程期间，在浮栅和程序门之间发生电子隧穿。

2. 发明授权

US06342431B2 Method for eliminating transfer gate sacrificial oxide 失效
标题翻译：消除传输门牺牲氧化物的方法
公开(公告)号：US06342431B2
公开(公告)日：2002-01-29
申请号：US09173089
申请日：1998-10-14
申请人： Kevin M. Houlihan , Jed H. Rankin
发明人： Kevin M. Houlihan , Jed H. Rankin
IPC分类号： H01L218238
CPC分类号： H01L21/76224 , H01L21/28167 , H01L21/3143 , H01L21/31612 , H01L21/823878 , H01L21/823892
摘要： A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the substrate using the oxide layer and the nitride layer, removing the silicon nitride layer, ion implanting dopant ions using the original oxide layer as a screen, into the substrate, and removing the oxide layer and forming a gate oxide layer over the substrate. Another method of forming an active area of a semiconductor device, includes using a pad oxide, remaining after removing a film layer thereover of an oxide/film mask stack, for a screen layer for well implants formed in the substrate, removing the oxide layer and forming a gate oxide over the substrate, following defining the well implants, without using a sacrificial oxide.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底上形成氧化物层，在氧化物层上形成氮化硅层，使用氧化物层和氮化物层在衬底中形成隔离区域，去除氮化硅层，使用原始氧化物层作为屏幕的离子注入掺杂剂离子进入衬底，并且去除氧化物层并在衬底上形成栅极氧化物层。形成半导体器件的有源区域的另一种方法包括使用衬垫氧化物，在除去氧化物/膜掩模叠层之上的膜层之后留下用于在衬底中形成的阱注入的屏蔽层，去除氧化物层和在不使用牺牲氧化物的情况下，在定义井注入之后，在衬底上形成栅极氧化物。

3. 发明授权

US08877596B2 Semiconductor devices with asymmetric halo implantation and method of manufacture 有权
标题翻译：具有不对称光晕植入的半导体器件及其制造方法
公开(公告)号：US08877596B2
公开(公告)日：2014-11-04
申请号：US12822426
申请日：2010-06-24
申请人： Darshana N. Bhagat , Thomas J. Dunbar , Yen Li Lim , Jed H. Rankin , Eva A. Shah
发明人： Darshana N. Bhagat , Thomas J. Dunbar , Yen Li Lim , Jed H. Rankin , Eva A. Shah
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L21/425
CPC分类号： H01L29/7835 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L21/823807 , H01L29/7833
摘要： a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the at least one of the gate structures.
摘要翻译：一种方法包括在一个或多个栅极结构上形成硬掩模。该方法还包括在硬掩模上形成光致抗蚀剂。该方法还包括在至少一个栅极结构上的光致抗蚀剂中形成开口。该方法还包括剥离暴露在开口中且位于至少一个栅极结构之上的硬掩模。该方法还包括去除光致抗蚀剂。该方法还包括在所述至少一个栅极结构的一侧上提供晕轮植入物。

4. 发明授权

US08815671B2 Use of contacts to create differential stresses on devices 有权
标题翻译：使用触点在器件上产生差分应力
公开(公告)号：US08815671B2
公开(公告)日：2014-08-26
申请号：US12892474
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76834 , H01L21/76877 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/665 , H01L29/6653 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.
摘要翻译：这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

5. 发明授权

US08609453B2 Low cost solar cell manufacture method employing a reusable substrate 失效
标题翻译：低成本太阳能电池制造方法采用可重复使用的基板
公开(公告)号：US08609453B2
公开(公告)日：2013-12-17
申请号：US12951601
申请日：2010-11-22
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/00
CPC分类号： H01L31/186 , H01L31/0248 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.
摘要翻译：描述了可重复使用的基板和用于形成单晶硅太阳能电池的方法。形成光伏电池的方法包括在单晶硅衬底上形成中间层，在中间层上形成单晶硅层，并在单晶硅层中形成电特征。该方法还包括在单晶硅层中形成开口，并且通过选择性地通过开口蚀刻中间层，从而将单晶硅层从衬底上分离出来。

6. 发明申请

US20130170012A1 MICROMIRRORS FOR COLOR ELECTRONIC PAPER AND DESIGN STRUCTURES FOR SAME 有权
标题翻译：用于彩色电子纸的微型计算机及其设计结构
公开(公告)号：US20130170012A1
公开(公告)日：2013-07-04
申请号：US13343395
申请日：2012-01-04
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G02B26/00
CPC分类号： G02B26/0841 , G02B5/201
摘要： Direct view color displays and design structures of direct view color displays. The direct view displays include micromirrors having un-tilted and tilted states and multiple color filters or color reflectors.
摘要翻译：直观视图彩色显示器和直观视图彩色显示器的设计结构。直视图显示器包括具有不倾斜和倾斜状态的微镜，以及多个滤色器或彩色反射器。

7. 发明授权

US08445965B2 Strained semiconductor devices and methods of fabricating strained semiconductor devices 有权
标题翻译：应变半导体器件和制造应变半导体器件的方法
公开(公告)号：US08445965B2
公开(公告)日：2013-05-21
申请号：US12940115
申请日：2010-11-05
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.
摘要翻译：一种制造结构的结构和方法。该结构包括半导体衬底的第一区域，其通过在衬底中形成的沟槽隔离与半导体衬底的第二区域分离; 第一个区域的第一个应力层; 在第二区域的第二个应力层; 第一应力层和第二应力层由间隙分开; 以及在第一和第二应力层上的钝化层，钝化层延伸并密封间隙。

8. 发明申请

US20130065370A1 Method for Fabricating Field Effect Transistor Devices with High-Aspect Ratio Mask 失效
标题翻译：制造具有高比例掩模的场效应晶体管器件的方法
公开(公告)号：US20130065370A1
公开(公告)日：2013-03-14
申请号：US13229154
申请日：2011-09-09
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28273 , H01L29/66825 , H01L29/785
摘要： A method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material layer over the resist material and exposed regions of the substrate, modifying a portion of the substrate, and removing the masking material layer and the resist material.
摘要翻译：在衬底上形成特征的方法包括在衬底上形成至少一层特征材料，在特征材料的至少一层上图案化光刻抗蚀剂材料，去除特征材料的部分以限定特征，沉积在抗蚀剂材料上的掩模材料层和衬底的暴露区域，修改衬底的一部分，以及去除掩模材料层和抗蚀剂材料。

9. 发明授权

US08389183B2 Chromeless phase-shifting photomask with undercut rim-shifting element 有权
标题翻译：无铬相移光掩模与底切轮辋移动元件
公开(公告)号：US08389183B2
公开(公告)日：2013-03-05
申请号：US12702787
申请日：2010-02-09
申请人： Brent A. Anderson , Jed H. Rankin
发明人： Brent A. Anderson , Jed H. Rankin
IPC分类号： G03F1/28 , G03F1/29 , G03F1/34
CPC分类号： G03F1/29 , G03F1/34
摘要： A phase-shifting photomask with a self aligned undercut rim-shifting element and methods for its manufacture are provided. One embodiment of the invention provides a method of manufacturing a phase-shifting photomask having a self aligned rim-shifting element, the method comprising: applying a patterning film to a first portion of a transparent substrate; etching the substrate to a depth to remove a second portion of the substrate not beneath the patterning film; etching the first portion of the substrate to undercut an area beneath the patterning film; and removing the patterning film, wherein the etched substrate forms a self-aligned undercut rim-shifting element.
摘要翻译：提供了具有自对准底切边缘移动元件的相移光掩模及其制造方法。本发明的一个实施例提供了一种制造具有自对准边缘移位元件的相移光掩模的方法，所述方法包括：将图案化膜施加到透明基板的第一部分; 将衬底蚀刻到深度以去除衬底的第二部分而不在图案化膜下方; 蚀刻基板的第一部分以削去图案化膜下方的区域; 并且去除所述图案化膜，其中所述蚀刻的衬底形成自对准底切轮辋移位元件。

10. 发明授权

US08216909B2 Field effect transistor with air gap dielectric 有权
标题翻译：具有气隙电介质的场效应晶体管
公开(公告)号：US08216909B2
公开(公告)日：2012-07-10
申请号：US12547529
申请日：2009-08-26
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

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