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1. 发明授权

US07521950B2 Wafer level I/O test and repair enabled by I/O layer 失效
标题翻译：通过I / O层启用晶圆级I / O测试和修复
公开(公告)号：US07521950B2
公开(公告)日：2009-04-21
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , G01R31/00 , G01N37/00 , G06F13/20 , G06F13/36 , G06F11/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

2. 发明申请

US20110106741A1 SYSTEM FOR ADDRESS-EVENT-REPRESENTATION NETWORK SIMULATION 有权
标题翻译：地址 - 事件代表网络模拟系统
公开(公告)号：US20110106741A1
公开(公告)日：2011-05-05
申请号：US12611968
申请日：2009-11-04
申请人： Monty M. Denneau , Daniel J. Friedman , Ralph Linsker , Mark B. Ritter
发明人： Monty M. Denneau , Daniel J. Friedman , Ralph Linsker , Mark B. Ritter
IPC分类号： G06F15/18 , G06N3/08
CPC分类号： H04L47/521
摘要： A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.
摘要翻译：提供了一种用于地址事件表示网络仿真的系统，方法和设计结构。该系统包括硬件结构，其具有被配置为模拟多个互连节点的多个互连的处理模块。为了模拟每个节点，硬件结构包括被配置为接收输入消息并且识别与输入消息的源相关联的权重的源表。硬件结构还包括状态管理逻辑，其被配置为根据所识别的权重更新节点状态，并响应于更新的节点状态生成输出信号。硬件结构进一步包括目标表，其被配置为响应于输出信号产生输出消息，识别目标以接收输出消息，并发送输出消息。硬件结构还可以包括被配置为组合关于输入消息和生成的输出信号的信息并且更新权重的学习逻辑。

3. 发明授权

US08429107B2 System for address-event-representation network simulation 有权
标题翻译：地址事件表示网络仿真系统
公开(公告)号：US08429107B2
公开(公告)日：2013-04-23
申请号：US12611968
申请日：2009-11-04
申请人： Monty M. Denneau , Daniel J. Friedman , Ralph Linsker , Mark B. Ritter
发明人： Monty M. Denneau , Daniel J. Friedman , Ralph Linsker , Mark B. Ritter
IPC分类号： G06F15/18 , G06N3/08
CPC分类号： H04L47/521
摘要： A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.
摘要翻译：提供了一种用于地址事件表示网络仿真的系统，方法和设计结构。该系统包括硬件结构，其具有被配置为模拟多个互连节点的多个互连的处理模块。为了模拟每个节点，硬件结构包括被配置为接收输入消息并且识别与输入消息的源相关联的权重的源表。硬件结构还包括状态管理逻辑，其被配置为根据所识别的权重更新节点状态，并响应于更新的节点状态生成输出信号。硬件结构进一步包括目标表，其被配置为响应于输出信号产生输出消息，识别目标以接收输出消息，并发送输出消息。硬件结构还可以包括被配置为组合关于输入消息和生成的输出信号的信息并且更新权重的学习逻辑。

4. 发明授权

US09203159B2 Phased-array transceiver 有权
标题翻译：相控阵收发器
公开(公告)号：US09203159B2
公开(公告)日：2015-12-01
申请号：US13371924
申请日：2012-02-13
申请人： Daniel J. Friedman , Xiaoxiong Gu , Duixian Liu , Arun S. Natarajan , Scott K. Reynolds , Alberto Valdes Garcia
发明人： Daniel J. Friedman , Xiaoxiong Gu , Duixian Liu , Arun S. Natarajan , Scott K. Reynolds , Alberto Valdes Garcia
IPC分类号： H01Q1/24 , H01Q21/06
CPC分类号： H01Q21/061 , H01L2224/16225 , H01Q21/065 , H01Q23/00 , H04B7/04 , Y10T29/49016
摘要： Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.
摘要翻译：公开了针对收发器设备的系统，方法，设备和设备。根据一种方法，选择电路封装的电路布局的一组部分的第一部分中的第一组天线位置。该方法还包括在电路布局的另一部分中选择另一组天线位置，使得另一组的所选择的天线位置的布置与先前选择的一组天线位置的选定天线位置的布置不同。迭代在另一部分中选择另一组位置，直到对天线总数进行选择。执行另一组的选择，使得另一部分中的连续未选定位置不超过预定数量的位置。此外，天线元件形成在所选择的位置以制造电路封装。

5. 发明授权

US08898097B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
标题翻译：可重构和可定制的神经网络通用电路
公开(公告)号：US08898097B2
公开(公告)日：2014-11-25
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

6. 发明授权

US08856055B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
公开(公告)号：US08856055B2
公开(公告)日：2014-10-07
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

7. 发明授权

US08779865B2 Ultra-compact PLL with wide tuning range and low noise 有权
标题翻译：超紧凑型PLL，调谐范围宽，噪音低
公开(公告)号：US08779865B2
公开(公告)日：2014-07-15
申请号：US13350981
申请日：2012-01-16
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
IPC分类号： H03B5/12 , H03L7/10
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译：振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。两个LC坦克被嵌套和切换。通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。

8. 发明授权

US08704566B2 Hybrid phase-locked loop architectures 有权
标题翻译：混合锁相环架构
公开(公告)号：US08704566B2
公开(公告)日：2014-04-22
申请号：US13608277
申请日：2012-09-10
申请人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/1072 , H03L7/087 , H03L7/089 , H03L7/093
摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.
摘要翻译：提供了锁相环（PLL）架构，例如具有单独的数字积分控制路径和模拟比例控制路径的混合PLL架构。可以使用包括与CMOS开关串联的电阻器的电荷泵电路来实现模拟比例控制路径，以产生用于调节施加到数字控制振荡器的控制电压的控制电流（例如，上/下控制电流）。可以用一系列在不同频率下操作的Σ-Δ调制器来实现数字积分控制路径，以将较高位数据信号转换为沿着数字积分控制路径的较低位数据信号。可以实现单相频率检测器来产生分别控制模拟比例和数字积分控制路径的控制信号。

9. 发明申请

US20140070856A1 HYBRID PHASE-LOCKED LOOP ARCHITECTURES 有权
标题翻译：混合相位锁定环路结构
公开(公告)号：US20140070856A1
公开(公告)日：2014-03-13
申请号：US13611008
申请日：2012-09-12
申请人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/107
CPC分类号： H03L7/1072 , H03L7/087 , H03L7/089 , H03L7/093
摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.
摘要翻译：提供了锁相环（PLL）架构，例如具有单独的数字积分控制路径和模拟比例控制路径的混合PLL架构。可以使用包括与CMOS开关串联的电阻器的电荷泵电路来实现模拟比例控制路径，以产生用于调节施加到数字控制振荡器的控制电压的控制电流（例如，上/下控制电流）。可以用一系列在不同频率下操作的Σ-Δ调制器来实现数字积分控制路径，以将较高位数据信号转换为沿着数字积分控制路径的较低位数据信号。可以实现单相频率检测器来产生分别控制模拟比例和数字积分控制路径的控制信号。

10. 发明申请

US20120317062A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
标题翻译：神经网络可重构和可定制的一般用途电路
公开(公告)号：US20120317062A1
公开(公告)日：2012-12-13
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. BREZZO , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. BREZZO , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

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