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1. 发明公开

US20230187005A1 TESTING METHOD FOR PACKAGED CHIP, TESTING SYSTEM FOR PACKAGED CHIP, COMPUTER DEVICE AND STORAGE MEDIUM 审中-公开
公开(公告)号：US20230187005A1
公开(公告)日：2023-06-15
申请号：US17615566
申请日：2021-05-17
申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.
发明人： Cheng-Jer YANG
IPC分类号： G11C29/10
CPC分类号： G11C29/10 , G11C2029/1206
摘要： The present application relates to a testing method for a packaged chip, a testing system for a packaged chip, a computer device and a storage medium. The method includes following steps: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time, and subsequent testing will be performed continuously. Moreover, since the products satisfying the requirements can be screened out in the bum-in test process, compared with the prior art, the test cost is reduced, and the test efficiency is improved.

2. 发明申请

US20190108868A1 METHOD OF SELF-TESTING AND REUSING OF REFERENCE CELLS IN A MEMORY ARCHITECTURE 审中-公开
公开(公告)号：US20190108868A1
公开(公告)日：2019-04-11
申请号：US15726084
申请日：2017-10-05
申请人： Gyrfalcon Technology Inc.
发明人： Chyu-Jiuh Torng , Lin Yang , Qi Dong , Daniel H. Liu
IPC分类号： G11C11/4078 , G11C11/02 , G06N99/00 , G06F15/18
CPC分类号： G11C11/4078 , G06N3/0454 , G06N20/00 , G11C11/02 , G11C29/028 , G11C29/08 , G11C29/24 , G11C29/46 , G11C2029/0401 , G11C2029/1206 , G11C2029/4402
摘要： An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

3. 发明申请

US20180233193A1 Process Variation Detector 审中-公开
公开(公告)号：US20180233193A1
公开(公告)日：2018-08-16
申请号：US15434659
申请日：2017-02-16
申请人： ARM LIMITED
发明人： AKSHAY KUMAR , SAIKAT KUMAR BANIK
IPC分类号： G11C11/419 , H01L27/092
CPC分类号： H01L27/0922 , G11C5/025 , G11C11/417 , G11C29/12005 , G11C29/26 , G11C29/50004 , G11C2029/0403 , G11C2029/1206 , G11C2029/5002 , G11C2029/5004
摘要： Various implementations described herein are directed to an integrated circuit having a memory cell array disposed in a first area of the integrated circuit. The memory cell array may include memory cells with first transistors of multiple types. The integrated circuit may include a process sensor disposed in a second area of the integrated circuit that is different than the first area. The process sensor may include a process detector having second transistors of the multiple types that are separate from the first transistors. The second transistors of the process detector may be arranged for detecting process variation of the memory cells of the memory cell array.

4. 发明申请

US20170084351A1 INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR 审中-公开
公开(公告)号：US20170084351A1
公开(公告)日：2017-03-23
申请号：US15368402
申请日：2016-12-02
申请人： INTEL CORPORATION
发明人： Bruce QUERBACH , William K. LUI , David G. ELLIS , David J. ZIMMERMAN , Theodore Z. SCHOENBORN , Christopher W. HAMPSON , Ifar WAN , Yulan ZHANG
IPC分类号： G11C29/38 , G11C29/44 , G11C29/36
CPC分类号： G11C29/38 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/36 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C29/783 , G11C2029/1202 , G11C2029/1204 , G11C2029/1206 , G11C2029/1208 , G11C2029/3602 , G11C2029/4402
摘要： In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.

5. 发明授权

US09324380B2 Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths 有权
标题翻译：能够通过各种路径输入信号的叠层半导体装置和半导体系统
公开(公告)号：US09324380B2
公开(公告)日：2016-04-26
申请号：US14329213
申请日：2014-07-11
申请人： SK hynix Inc.
发明人： Sang Jin Byeon , Jae Bum Ko , Young Jun Ku
IPC分类号： G11C5/04 , G11C29/12 , G11C29/26 , H01L25/18 , H01L23/00 , H01L25/065 , G11C29/18 , G11C7/10
CPC分类号： G11C5/04 , G11C7/1045 , G11C29/1201 , G11C29/18 , G11C29/26 , G11C2029/1206 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1441 , H01L2924/1443 , H01L2924/15192 , H01L2924/157
摘要： A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion.
摘要翻译：半导体装置包括控制信号接收部。控制信号接收部分可以通过从栈芯片测试部分，控制信号接口部分和测试设置部分之一接收命令信号和地址信号来设置与存储芯片的操作有关的信息。

6. 发明申请

US20150187441A1 DATA PATTERN GENERATION FOR I/O TESTING OF MULTILEVEL INTERFACES 有权
标题翻译：用于多路接口I / O测试的数据模式生成
公开(公告)号：US20150187441A1
公开(公告)日：2015-07-02
申请号：US14144432
申请日：2013-12-30
申请人： QUALCOMM Incorporated
发明人： Timothy Mowry Hollis
IPC分类号： G11C29/36 , G06F11/263 , G06F11/27 , G11C29/12
CPC分类号： G11C29/36 , G06F11/263 , G06F11/27 , G11C29/022 , G11C29/12005 , G11C29/1201 , G11C2029/1206 , G11C2029/3602
摘要： One feature is a method of reading data from a plurality of pattern registers, generating a first output at a mapping register from the read data, generating a second output, different from the first output, at the mapping register from the read data, and generating a multi-level signal using the first and second outputs. In one embodiment, generating the first output is done by adding a first plurality of bits to a second plurality of bits, and generating the second output is done by adding the first plurality of bits to an inverse of the second plurality of bits.
摘要翻译：一个特征是从多个模式寄存器读取数据的方法，从读取的数据在映射寄存器处生成第一输出，在映射寄存器处产生与第一输出不同的第二输出与读取的数据，并产生使用第一和第二输出的多电平信号。在一个实施例中，通过将第一多个比特添加到第二多个比特来生成第一输出，并且通过将第一多个比特相加到第二多个比特的倒数来生成第二输出。

7. 发明授权

US09013908B2 Control scheme for 3D memory IC 有权
标题翻译： 3D存储器IC的控制方案
公开(公告)号：US09013908B2
公开(公告)日：2015-04-21
申请号：US13524980
申请日：2012-06-15
申请人： Meng-Fan Chang , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
发明人： Meng-Fan Chang , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
IPC分类号： G11C29/00 , G11C29/02 , G11C8/08 , G11C11/417 , G11C29/26 , G11C29/04 , G11C29/12
CPC分类号： G11C29/023 , G11C8/08 , G11C11/417 , G11C29/028 , G11C29/04 , G11C29/26 , G11C2029/1202 , G11C2029/1206 , G11C2029/2602
摘要： The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.
摘要翻译：本发明公开了一种包括主芯片和至少一个从芯片的3D存储器IC的控制方案。主芯片包括主存储器核心，第一本地定时器，I / O缓冲器，第一焊盘和第二焊盘。至少一个从芯片与主芯片堆叠。每个从芯片包括从存储器核心，第二本地定时器和第三焊盘。第一TSV耦合到第一焊盘和第三焊盘。逻辑控制电路层包括逻辑控制电路和第四焊盘，逻辑控制电路耦合到第四焊盘。第二TSV耦合到第二焊盘和第四焊盘。

8. 发明授权

US08890557B2 Built-in self-test method and structure 有权
标题翻译：内置自检方法和结构
公开(公告)号：US08890557B2
公开(公告)日：2014-11-18
申请号：US13443450
申请日：2012-04-10
申请人： Yoba Amoah , John J. Ellis-Monaghan , Roger C. Kuo , Molly J. Leitch , Zhihong Zhang
发明人： Yoba Amoah , John J. Ellis-Monaghan , Roger C. Kuo , Molly J. Leitch , Zhihong Zhang
IPC分类号： G01R31/3187
CPC分类号： G01R31/318511 , G01R31/2856 , G11C29/006 , G11C29/12 , G11C2029/1206
摘要： A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.
摘要翻译：一种半导体晶片的测试方法及相关结构。在各种实施例中，一种方法包括：将探针放置在半导体晶片上的第一芯片上; 测试划线自动内置自检（ABIST）为第一芯片寻找故障; 响应于确定第一芯片的ABIST而对半导体晶片上的后续芯片进行随后的划线ABIST的逐步测试不表示故障; 将探针点移动到随后的芯片，并且响应于确定随后芯片的ABIST指示故障，重新测试随后的划线ABIST; 以及响应于确定随后的scribiline的重新测试，测试另一后续划线ABIST用于半导体晶片上的另外的后续芯片，ABIST不指示后续划线ABIST中的故障。

9. 发明申请

US20120221911A1 EMBEDDED PROCESSOR 有权
标题翻译：嵌入式处理器
公开(公告)号：US20120221911A1
公开(公告)日：2012-08-30
申请号：US13465247
申请日：2012-05-07
申请人： Joe M. Jeddeloh
发明人： Joe M. Jeddeloh
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31917 , G01R31/3183 , G01R31/3187 , G06F11/2635 , G11C5/02 , G11C5/04 , G11C29/10 , G11C29/12 , G11C29/16 , G11C29/36 , G11C2029/0401 , G11C2029/1206 , G11C2029/3602
摘要： Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
摘要翻译：电子设备，系统以及操作和构建电子设备和/或系统的方法包括设置在逻辑芯片中的嵌入式处理器，以指导电子设备结构的自检以及布置在逻辑芯片，当电子器件结构耦合到逻辑芯片时。公开了附加装置，系统和方法。

10. 发明申请

US20120001175A1 SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING A COUPLING EFFECT OF A TEST-DISABLE TRANSMISSION LINE 有权
标题翻译：能够抑制测试传输线的耦合效应的半导体器件
公开(公告)号：US20120001175A1
公开(公告)日：2012-01-05
申请号：US13229086
申请日：2011-09-09
申请人： Jeong-Yoon AHN , Ji-Eun Jang , Young-Jun Ku
发明人： Jeong-Yoon AHN , Ji-Eun Jang , Young-Jun Ku
IPC分类号： H01L23/58
CPC分类号： G11C29/46 , G11C29/02 , G11C29/025 , G11C29/1201 , G11C2029/1206
摘要： Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.
摘要翻译：半导体器件和半导体存储器件包括多个内部电路，其被配置为响应于它们各自的测试模式信号执行测试操作;以及多个测试模式控制单元，被配置为响应于所述内部电路被禁用而控制内部电路的测试操作一个测试信号。

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