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1. 发明授权

US08298906B2 Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch 失效
标题翻译：通过硅经过（TSV）蚀刻的RIE滞后形成的沟槽去耦电容器
公开(公告)号：US08298906B2
公开(公告)日：2012-10-30
申请号：US12511545
申请日：2009-07-29
申请人： Kerry Bernstein , Francis Roger White
发明人： Kerry Bernstein , Francis Roger White
IPC分类号： H01L21/20
CPC分类号： H01L21/3065 , H01L21/76898 , H01L29/66181
摘要： A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag.
摘要翻译：使用通过硅通孔（TSV）蚀刻的RIE滞后来形成沟槽去耦电容器。一种方法包括在单个RIE工艺中蚀刻晶片中的通孔沟槽和电容器沟槽。通孔沟槽具有第一深度，并且由于RIE滞后，电容器沟槽具有小于第一深度的第二深度。

2. 发明授权

US07989865B2 Deep trench capacitor for SOI CMOS devices for soft error immunity 有权
标题翻译：用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度
公开(公告)号：US07989865B2
公开(公告)日：2011-08-02
申请号：US12200538
申请日：2008-08-28
申请人： John Edward Barth, Jr. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
发明人： John Edward Barth, Jr. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

3. 发明申请

US20100052026A1 DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY 有权
标题翻译：用于软错误免疫的SOI CMOS器件的深度TRENCH电容器
公开(公告)号：US20100052026A1
公开(公告)日：2010-03-04
申请号：US12200538
申请日：2008-08-28
申请人： John Edward Barth, JR. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
发明人： John Edward Barth, JR. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

4. 发明授权

US08729549B2 Test structure and methodology for three-dimensional semiconductor structures 有权
标题翻译：三维半导体结构的测试结构和方法
公开(公告)号：US08729549B2
公开(公告)日：2014-05-20
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： H01L23/58
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译：在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。可以在完成所有至少一个功能层的所有制造之后执行C4键合。不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

5. 发明申请

US20140043757A1 ELECTRO-RHEOLOGICAL MICRO-CHANNEL ANISOTROPIC COOLED INTEGRATED CIRCUITS AND METHODS THEREOF 有权
标题翻译：电 - 流变微通道各向异性冷却集成电路及其方法
公开(公告)号：US20140043757A1
公开(公告)日：2014-02-13
申请号：US13568248
申请日：2012-08-07
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie
IPC分类号： G05D23/00 , H05K7/20
CPC分类号： G05D23/1919 , G06F1/206 , H01L23/38 , H01L23/473 , H01L2224/16225 , H01L2924/1305 , H01L2924/15174 , H01L2924/15311 , H05K7/20272 , H05K7/20281 , H05K7/20518 , H01L2924/00
摘要： An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature.
摘要翻译：具有形成在集成电路芯片的多个区域中的微通道的集成电路芯片和冷却集成电路芯片的方法。该方法包括对于多个区域的任何区域，只有当该区域的温度超过第一规定温度并且阻止冷却剂流过该区域的微通道时，冷却剂才能流过该区域的微通道，该区域的温度低于第二规定温度。

6. 发明授权

US08575964B2 Inactivity triggered self clocking logic family 有权
标题翻译：不活动触发自我计时逻辑家族
公开(公告)号：US08575964B2
公开(公告)日：2013-11-05
申请号：US13426776
申请日：2012-03-22
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
IPC分类号： H03K19/00
CPC分类号： H03K19/0966 , H03K19/0013
摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
摘要翻译：电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中只有在本地逻辑设备中已经满足设置时间之后）。这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

7. 发明授权

US08343814B2 Compact multi-port cam cell implemented in 3D vertical integration 有权
标题翻译：紧凑型多端口凸轮单元，实现3D垂直整合
公开(公告)号：US08343814B2
公开(公告)日：2013-01-01
申请号：US12542235
申请日：2009-08-17
申请人： Robert J. Bucki , Jagreet S. Atwal , Joseph S. Barnes , Kerry Bernstein , Eric Robinson
发明人： Robert J. Bucki , Jagreet S. Atwal , Joseph S. Barnes , Kerry Bernstein , Eric Robinson
IPC分类号： H01L21/335
CPC分类号： H01L25/0657 , G11C15/00 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L2221/68368 , H01L2224/24226 , H01L2224/80896 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.
摘要翻译：提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。多端口CAM单元在本发明中是通过利用三维积分来实现的，其中多个有源电路层是垂直堆叠的，并且使用垂直排列的互连将器件从堆叠层之一连接到另一层叠层中的另一个器件。通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。

8. 发明申请

US20120326333A1 SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT 有权
标题翻译：用于冗余和改进的半导体芯片堆叠
公开(公告)号：US20120326333A1
公开(公告)日：2012-12-27
申请号：US13607680
申请日：2012-09-08
申请人： Kerry Bernstein , Philip G. Emma , Michael Ignatowski
发明人： Kerry Bernstein , Philip G. Emma , Michael Ignatowski
IPC分类号： H01L25/00
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.
摘要翻译：包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成提供第一芯片组件的完全功能实例的功能的功能块。层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。

9. 发明授权

US08263472B2 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
标题翻译：用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管
公开(公告)号：US08263472B2
公开(公告)日：2012-09-11
申请号：US13324486
申请日：2011-12-13
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/76
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层，第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

10. 发明授权

US08234554B2 Soft error correction in sleeping processors 有权
标题翻译：睡眠处理器中的软错误校正
公开(公告)号：US08234554B2
公开(公告)日：2012-07-31
申请号：US12170462
申请日：2008-07-10
申请人： Kerry Bernstein , Norman J. Rohrer
发明人： Kerry Bernstein , Norman J. Rohrer
IPC分类号： H03M13/00
CPC分类号： H03M13/15 , G06F11/1008 , H03M13/098 , H03M13/13 , H03M13/1505 , H03M13/19
摘要： An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.
摘要翻译：在处理器进入睡眠模式之前，将物理逻辑寄存器和锁存内容逐行生成在处理器内的处理器内，生成错误校正码，并检查后来生成的校验码位处理器唤醒时出现软错误，例如作为上电顺序的一部分。

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