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1. 发明申请

US20100052026A1 DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY 有权
标题翻译：用于软错误免疫的SOI CMOS器件的深度TRENCH电容器
公开(公告)号：US20100052026A1
公开(公告)日：2010-03-04
申请号：US12200538
申请日：2008-08-28
申请人： John Edward Barth, JR. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
发明人： John Edward Barth, JR. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

2. 发明授权

US07989865B2 Deep trench capacitor for SOI CMOS devices for soft error immunity 有权
标题翻译：用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度
公开(公告)号：US07989865B2
公开(公告)日：2011-08-02
申请号：US12200538
申请日：2008-08-28
申请人： John Edward Barth, Jr. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
发明人： John Edward Barth, Jr. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

3. 发明授权

US08298906B2 Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch 失效
标题翻译：通过硅经过（TSV）蚀刻的RIE滞后形成的沟槽去耦电容器
公开(公告)号：US08298906B2
公开(公告)日：2012-10-30
申请号：US12511545
申请日：2009-07-29
申请人： Kerry Bernstein , Francis Roger White
发明人： Kerry Bernstein , Francis Roger White
IPC分类号： H01L21/20
CPC分类号： H01L21/3065 , H01L21/76898 , H01L29/66181
摘要： A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag.
摘要翻译：使用通过硅通孔（TSV）蚀刻的RIE滞后来形成沟槽去耦电容器。一种方法包括在单个RIE工艺中蚀刻晶片中的通孔沟槽和电容器沟槽。通孔沟槽具有第一深度，并且由于RIE滞后，电容器沟槽具有小于第一深度的第二深度。

4. 发明授权

US06420777B2 Dual layer etch stop barrier 失效
标题翻译：双层蚀刻停止屏障
公开(公告)号：US06420777B2
公开(公告)日：2002-07-16
申请号：US09031251
申请日：1998-02-26
申请人： Chung Hon Lam , Eric Seung Lee , Francis Roger White
发明人： Chung Hon Lam , Eric Seung Lee , Francis Roger White
IPC分类号： H01L2358
CPC分类号： H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/31116 , H01L21/3185 , Y10S438/97
摘要： A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.
摘要翻译：提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。具有小于约0.8且优选化学计量量为0.75的六至奈比（x：y）的氮化硅（SixNy）阻挡层对正移动离子污染提供优异的回弹性，但蚀刻选择性差。然而，六至氮（x：y）的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性，但对于移动离子污染的正面阻挡性差。在掺杂硅衬底上形成氮化硅屏障，该阻挡层具有两个部分。一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性，并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。与硅衬底相邻的一个部分的硅氮比小于约0.8。在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。优选地，两个部分一起为约50至约100纳米厚。

5. 发明授权

US5675185A Semiconductor structure incorporating thin film transistors with undoped cap oxide layers 失效
标题翻译：结合具有未掺杂的帽氧化物层的薄膜晶体管的半导体结构
公开(公告)号：US5675185A
公开(公告)日：1997-10-07
申请号：US537219
申请日：1995-09-29
申请人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Bret Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
发明人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Bret Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
IPC分类号： H01L27/06 , H01L27/11 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/1108 , H01L27/0688 , H01L2924/0002
摘要： An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.
摘要翻译：公开了一种改进的场效应晶体管（FET）结构。它包括第一绝缘体层，其包含延伸穿过该层的至少一个主级螺柱; 设置在绝缘体层上并与每个螺柱的上部区域邻接的未掺杂的帽氧化物层; 设置在未掺杂的帽氧化物层上的初级级薄膜晶体管（TFT）; 以及设置在TFT上的平坦化氧化物层。多个TFT可以垂直堆叠，并连接到其他级别的螺柱和金属互连层。本发明的另一个实施例包括在钨型螺柱的表面上使用保护性界面盖。 FET结构可以用作静态随机存取存储器（SRAM）单元的组件。还公开了相关过程。

6. 发明授权

US07812388B2 Deep trench capacitor and method of making same 有权
标题翻译：深沟槽电容器及其制作方法
公开(公告)号：US07812388B2
公开(公告)日：2010-10-12
申请号：US11767616
申请日：2007-06-25
申请人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M Shank , Francis Roger White
发明人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M Shank , Francis Roger White
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/945 , H01L28/40
摘要： A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.
摘要翻译：沟槽电容器和形成沟槽电容器的方法。所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

7. 发明授权

US06680259B2 Dual layer etch stop barrier 有权
标题翻译：双层蚀刻停止屏障
公开(公告)号：US06680259B2
公开(公告)日：2004-01-20
申请号：US10413087
申请日：2003-04-14
申请人： Chung Hon Lam , Eric Seung Lee , Francis Roger White
发明人： Chung Hon Lam , Eric Seung Lee , Francis Roger White
IPC分类号： H01L21302
CPC分类号： H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/31116 , H01L21/3185 , Y10S438/97
摘要： A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.
摘要翻译：提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。具有小于约0.8且优选化学计量量为0.75的六至奈比（x：y）的氮化硅（SixNy）阻挡层对正移动离子污染提供优异的回弹性，但蚀刻选择性差。然而，六至氮（x：y）的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性，但对于移动离子污染的正面阻挡性差。在掺杂硅衬底上形成氮化硅屏障，该阻挡层具有两个部分。一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性，并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。与硅衬底相邻的一个部分的硅氮比小于约0.8。在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。优选地，两个部分一起为约50至约100纳米厚。

8. 发明授权

US6140171A FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication 失效
标题翻译： FET器件包含用于局部互连的导电侧壁间隔件及其制造方法
公开(公告)号：US6140171A
公开(公告)日：2000-10-31
申请号：US233549
申请日：1999-01-20
申请人： Archibald John Allen , Jerome Brett Lasky , Randy William Mann , John Joseph Pekarik , Jed Hickory Rankin , Edward William Sengle , Francis Roger White
发明人： Archibald John Allen , Jerome Brett Lasky , Randy William Mann , John Joseph Pekarik , Jed Hickory Rankin , Edward William Sengle , Francis Roger White
IPC分类号： H01L21/336 , H01L21/768 , H01L29/417
CPC分类号： H01L29/66659 , H01L21/76895 , H01L29/41775 , H01L29/6656 , Y10S257/90 , Y10S257/903
摘要： A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spacer conductor on the sidewall dielectric contacting one of the diffusion regions but not both of the diffusion regions of one device is provided along with a method for its fabrication. The conductive spacer connects diffusions of adjacent devices that share a common gate electrode.
摘要翻译：一种FET器件，包括半导体衬底; 由沟道区分隔的衬底中的扩散区; 栅极与沟道区域和扩散区域的一部分重叠并且通过栅极电介质与衬底分离; 以及在所述栅极的侧壁上的侧壁电介质; 并且与其制造方法一起提供了与一个装置的扩散区域之一而不是两个扩散区域的侧壁电介质上的侧壁间隔导体。导电间隔物连接共享公共栅电极的相邻器件的扩散。

9. 发明申请

US20090100388A1 DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME 失效
标题翻译：深度电容电容器及其制造方法
公开(公告)号：US20090100388A1
公开(公告)日：2009-04-16
申请号：US11872787
申请日：2007-10-16
申请人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M. Shank , Francis Roger White
发明人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M. Shank , Francis Roger White
IPC分类号： G06F9/45
CPC分类号： H01L29/945 , H01L29/66181
摘要： A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.
摘要翻译：沟槽电容器，形成沟槽电容器的方法以及沟槽电容器的设计结构。所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

10. 发明授权

US07694262B2 Deep trench capacitor and method of making same 失效
标题翻译：深沟槽电容器及其制作方法
公开(公告)号：US07694262B2
公开(公告)日：2010-04-06
申请号：US11872787
申请日：2007-10-16
申请人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M. Shank , Francis Roger White
发明人： Timothy Wayne Kemerer , Robert Mark Rassel , Steven M. Shank , Francis Roger White
IPC分类号： G06F17/50
CPC分类号： H01L29/945 , H01L29/66181
摘要： A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.
摘要翻译：沟槽电容器，形成沟槽电容器的方法以及沟槽电容器的设计结构。所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

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