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    • 1. 发明授权
    • Dual layer etch stop barrier
    • 双层蚀刻停止屏障
    • US06420777B2
    • 2002-07-16
    • US09031251
    • 1998-02-26
    • Chung Hon LamEric Seung LeeFrancis Roger White
    • Chung Hon LamEric Seung LeeFrancis Roger White
    • H01L2358
    • H01L21/0217H01L21/022H01L21/02271H01L21/31116H01L21/3185Y10S438/97
    • A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.
    • 提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。 具有小于约0.8且优选化学计量量为0.75的六至奈比(x:y)的氮化硅(SixNy)阻挡层对正移动离子污染提供优异的回弹性,但蚀刻选择性差。 然而,六至氮(x:y)的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性,但对于移动离子污染的正面阻挡性差。 在掺杂硅衬底上形成氮化硅屏障,该阻挡层具有两个部分。 一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性,并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。 与硅衬底相邻的一个部分的硅氮比小于约0.8。 在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。 优选地,两个部分一起为约50至约100纳米厚。
    • 5. 发明申请
    • DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME
    • 深度电容电容器及其制造方法
    • US20090100388A1
    • 2009-04-16
    • US11872787
    • 2007-10-16
    • Timothy Wayne KemererRobert Mark RasselSteven M. ShankFrancis Roger White
    • Timothy Wayne KemererRobert Mark RasselSteven M. ShankFrancis Roger White
    • G06F9/45
    • H01L29/945H01L29/66181
    • A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.
    • 沟槽电容器,形成沟槽电容器的方法以及沟槽电容器的设计结构。 所述沟槽电容器包括:单晶硅衬底中的沟槽,在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板,其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。
    • 8. 发明授权
    • Deep trench capacitor and method of making same
    • 深沟槽电容器及其制作方法
    • US07812388B2
    • 2010-10-12
    • US11767616
    • 2007-06-25
    • Timothy Wayne KemererRobert Mark RasselSteven M ShankFrancis Roger White
    • Timothy Wayne KemererRobert Mark RasselSteven M ShankFrancis Roger White
    • H01L27/108H01L29/94
    • H01L29/945H01L28/40
    • A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.
    • 沟槽电容器和形成沟槽电容器的方法。 所述沟槽电容器包括:单晶硅衬底中的沟槽,在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板,其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。
    • 9. 发明授权
    • Dual layer etch stop barrier
    • 双层蚀刻停止屏障
    • US06680259B2
    • 2004-01-20
    • US10413087
    • 2003-04-14
    • Chung Hon LamEric Seung LeeFrancis Roger White
    • Chung Hon LamEric Seung LeeFrancis Roger White
    • H01L21302
    • H01L21/0217H01L21/022H01L21/02271H01L21/31116H01L21/3185Y10S438/97
    • A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.
    • 提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。 具有小于约0.8且优选化学计量量为0.75的六至奈比(x:y)的氮化硅(SixNy)阻挡层对正移动离子污染提供优异的回弹性,但蚀刻选择性差。 然而,六至氮(x:y)的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性,但对于移动离子污染的正面阻挡性差。 在掺杂硅衬底上形成氮化硅屏障,该阻挡层具有两个部分。 一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性,并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。 与硅衬底相邻的一个部分的硅氮比小于约0.8。 在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。 优选地,两个部分一起为约50至约100纳米厚。
    • 10. 发明授权
    • Deep trench capacitor and method of making same
    • 深沟槽电容器及其制作方法
    • US07694262B2
    • 2010-04-06
    • US11872787
    • 2007-10-16
    • Timothy Wayne KemererRobert Mark RasselSteven M. ShankFrancis Roger White
    • Timothy Wayne KemererRobert Mark RasselSteven M. ShankFrancis Roger White
    • G06F17/50
    • H01L29/945H01L29/66181
    • A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.
    • 沟槽电容器,形成沟槽电容器的方法以及沟槽电容器的设计结构。 所述沟槽电容器包括:单晶硅衬底中的沟槽,在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板,其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。