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1. 发明授权

US6075832A Method and apparatus for deskewing clock signals 失效
标题翻译：用于校正时钟信号的方法和装置
公开(公告)号：US6075832A
公开(公告)日：2000-06-13
申请号：US946671
申请日：1997-10-07
申请人： George Geannopoulos , Keng L. Wong , Greg F. Taylor , Xia Dai
发明人： George Geannopoulos , Keng L. Wong , Greg F. Taylor , Xia Dai
IPC分类号： G06F1/10 , H03D3/24 , H03D13/00 , H03L7/00 , H03L7/081 , H03L7/087
CPC分类号： H03L7/087 , G06F1/10 , H03L7/0814
摘要： An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.
摘要翻译：一种在同步数字系统中对时钟信号进行偏移校正的装置。该装置包含相位检测电路，其接收多个时钟信号，并根据这些时钟信号之间的相位关系产生输出。然后，控制器接收相位检测器的输出，并且基于相位检测器的输出和来自延迟移位寄存器的位确定多个时钟信号中的哪一个需要调整。控制器将延迟信号发送到多个延迟电路中的一个，其修改控制器确定需要调整的时钟信号的延迟。

2. 发明授权

US06985041B2 Clock generating circuit and method 失效
公开(公告)号：US06985041B2
公开(公告)日：2006-01-10
申请号：US10136390
申请日：2002-05-02
申请人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton
发明人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton
IPC分类号： H03B27/00
CPC分类号： G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/15013
摘要： A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.

3. 发明授权

US4638189A Fast and gate with programmable output polarity 失效
标题翻译：快速和门极可编程输出
公开(公告)号：US4638189A
公开(公告)日：1987-01-20
申请号：US626377
申请日：1984-06-29
申请人： George Geannopoulos , Cyrus Tsui , Mark Fitzpatrick , Andy Chan
发明人： George Geannopoulos , Cyrus Tsui , Mark Fitzpatrick , Andy Chan
IPC分类号： H03K19/177 , H03K17/66 , H03K19/173 , H03K19/20 , G06F11/28 , H03K19/003 , H03K19/082
CPC分类号： H03K19/1736 , H03K17/666
摘要： The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead. Thus, either the once inverted signal is provided to the output lead or the twice inverted signal is provided to the output lead.
摘要翻译：本发明以N逻辑输入信号的逻辑和功能组合，其中N是大于或等于1的选择的正整数，并且可编程地提供直接AND输出信号或NAND输出信号。本发明使用数据路径中的最小数量的组件，逻辑输入引线和逻辑输出引线之间来实现。数据路径中的最小组件减少了由电路引入的传播延迟。本发明通过提供连接到同一组N个逻辑输入信号的两个与门来实现这一点。一个与门的输出信号由具有使能/禁止输入引线的反相器反相。另一个与门的输出信号由两个反相器反相两次。第二个反相器具有使能/禁止输入引线。提供了用于通过使能/禁止输入引线独占地使能两个逆变器中的一个或另一个的装置。因此，将一次反相信号提供给输出引线，或将两次反相信号提供给输出引线。

4. 发明申请

US20080082282A1 Accurate on-die temperature measurement using remote sensing 失效
标题翻译：使用遥感精确的片上温度测量
公开(公告)号：US20080082282A1
公开(公告)日：2008-04-03
申请号：US11540002
申请日：2006-09-29
申请人： David Duarte , George Geannopoulos , Usman Mughal , Venkatesh Prasanna , Kedar Mangrulkar , Mathew Nazareth
发明人： David Duarte , George Geannopoulos , Usman Mughal , Venkatesh Prasanna , Kedar Mangrulkar , Mathew Nazareth
IPC分类号： G06F19/00
CPC分类号： G01K7/015
摘要： An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.
摘要翻译：本发明的实施例是用于热感测的技术。感测结构根据模具上的第一位置处的局部温度产生响应。传感器芯通过路由线耦合到感测结构，以提供来自响应的局部温度的测量。传感器芯位于远离第一位置的第二位置，并且由位于第二位置附近的模拟电源电压源供电。

5. 发明授权

US07512514B2 Accurate on-die temperature measurement using remote sensing 失效
标题翻译：使用遥感精确的片上温度测量
公开(公告)号：US07512514B2
公开(公告)日：2009-03-31
申请号：US11540002
申请日：2006-09-29
申请人： David Duarte , George Geannopoulos , Usman Mughal , Venkatesh Prasanna , Kedar Mangrulkar , Mathew Nazareth
发明人： David Duarte , George Geannopoulos , Usman Mughal , Venkatesh Prasanna , Kedar Mangrulkar , Mathew Nazareth
IPC分类号： H01L35/00
CPC分类号： G01K7/015
摘要： An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.
摘要翻译：本发明的实施例是用于热感测的技术。感测结构根据模具上的第一位置处的局部温度产生响应。传感器芯通过路由线耦合到感测结构，以提供来自响应的局部温度的测量。传感器芯位于远离第一位置的第二位置，并且由位于第二位置附近的模拟电源电压源供电。

6. 发明申请

US20090079406A1 High-voltage tolerant low-dropout dual-path voltage regulator with optimized regulator resistance and supply rejection 审中-公开
标题翻译：具有优化的稳压器电阻和电源抑制的高耐压低压差双通道电压调节器
公开(公告)号：US20090079406A1
公开(公告)日：2009-03-26
申请号：US11902922
申请日：2007-09-26
申请人： Chaodan Deng , Nasser A. Kurd , George Geannopoulos
发明人： Chaodan Deng , Nasser A. Kurd , George Geannopoulos
IPC分类号： G05F5/08
CPC分类号： G05F1/565
摘要： A voltage regulator includes an amplifier having first and second outputs, a feedback path coupled between a first input and the first output of the amplifier, and a feed-forward path between the second output of the amplifier and a switch coupled to a reference potential. In operation, a first control signal from the second output of the amplifier is generated based on a comparison of a reference signal and a feedback signal into the first input of the amplifier. The first control signal controls the switch to maintain a substantially constant supply voltage. A second control signal is generated along the feedback path to control controls the amount of supply voltage.
摘要翻译：电压调节器包括具有第一和第二输出的放大器，耦合在第一输入和放大器的第一输出之间的反馈路径，以及放大器的第二输出端与耦合到参考电位的开关之间的前馈路径。在操作中，基于放大器的第一输入端的参考信号和反馈信号的比较，产生来自放大器的第二输出的第一控制信号。第一控制信号控制开关以维持基本恒定的电源电压。沿着反馈路径产生第二控制信号以控制电源电压的量。

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