专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6060748A Semiconductor integrated circuit device using a silicon-on-insulator substrate 失效
标题翻译：使用绝缘体上硅衬底的半导体集成电路器件
公开(公告)号：US6060748A
公开(公告)日：2000-05-09
申请号：US997508
申请日：1997-12-23
申请人： Ken Uchida , Akira Toriumi , Akiko Ohata , Junji Koga
发明人： Ken Uchida , Akira Toriumi , Akiko Ohata , Junji Koga
IPC分类号： H01L21/84 , H01L23/528 , H01L27/12 , H01L25/00 , H01L29/00
CPC分类号： H01L23/5286 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor integrated circuit (IC) device has a silicon-on-insulator substrate having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a silicon layer formed on the insulating film. The semiconductor IC device includes at least one semiconductor device formed on the semiconductor substrate, and at least one semiconductor device formed on the silicon layer and operated with a power-supply voltage different from a power-supply voltage for the semiconductor device formed on the semiconductor substrate.
摘要翻译：半导体集成电路（IC）器件具有绝缘体上硅衬底，其具有半导体衬底，形成在半导体衬底上的绝缘膜和形成在绝缘膜上的硅层。半导体IC器件包括形成在半导体衬底上的至少一个半导体器件和形成在硅层上的至少一个半导体器件，并且以形成在半导体上的半导体器件的电源电压不同的电源电压来操作基质。

2. 发明授权

US06690030B2 Semiconductor device with negative differential resistance characteristics 失效
标题翻译：具有负差分电阻特性的半导体器件
公开(公告)号：US06690030B2
公开(公告)日：2004-02-10
申请号：US09798923
申请日：2001-03-06
申请人： Junji Koga , Ken Uchida , Ryuji Ohba , Akira Toriumi
发明人： Junji Koga , Ken Uchida , Ryuji Ohba , Akira Toriumi
IPC分类号： H01L2940
CPC分类号： H01L27/1104 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/511 , H01L29/7881
摘要： A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load. The negative differential resistance and the load are serially connected together between a low-voltage power supply (ground potential) Vss and a high-voltage power supply Vdd, thus enabling forming a transistor with a built-in bistable circuit. Potential information of the first polysilicon film for use as a data storage node is read with a transistor amplification applied thereto. Thus, data read is performed at high speeds. Simultaneously, a current flowing between the power supplies is suppressed to a lower level, thereby minimizing power consumption in wait modes.
摘要翻译：形成在硅衬底表面上的栅极氧化膜的厚度部分地减小或者在其源区域上的指定部分“薄化”。在栅极区域中，以层叠的顺序形成包括p型导电体的第一多晶硅或“多晶硅”膜，隧道氧化物膜和第二p型多晶硅膜的多层结构。源极区域和第一多晶硅膜构成了高浓度杂质掺杂的pn结，其间铺设有薄的氧化硅膜，提供了也称为Esaki二极管的隧道二极管。二极管用于负差分电阻。此外，第一和第二多晶硅膜之间的部分是用作负载的非线性隧道电阻器。负的差分电阻和负载在低压电源（接地电位）Vss和高压电源Vdd之间串联连接在一起，从而能够形成具有内置双稳态电路的晶体管。读取用作数据存储节点的第一多晶硅膜的电位信息，并施加晶体管放大。因此，高速执行数据读取。同时，在电源之间流动的电流被抑制到较低的电平，从而使等待模式中的功耗最小化。

3. 发明申请

US20080315183A1 SEMICONDUCTOR DEVICE WITH CARBON NANOTUBE CHANNEL AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有碳纳米管通道的半导体器件及其制造方法
公开(公告)号：US20080315183A1
公开(公告)日：2008-12-25
申请号：US12052229
申请日：2008-03-20
申请人： Atsuhiro KINOSHITA , Yoshifumi Nishi , Ken Uchida , Junji Koga
发明人： Atsuhiro KINOSHITA , Yoshifumi Nishi , Ken Uchida , Junji Koga
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L51/105 , B82Y10/00 , H01L51/0048 , H01L51/0512 , H01L51/0541 , H01L51/0545
摘要： A high-performance semiconductor device having a channel region structured from a carbon nanotube (CNT) for reducing or minimizing a drain leakage current is provided. This semiconductor device includes, in addition to the CNT-formed channel region, a gate electrode formed to overlie the channel region with a gate insulation film sandwiched therebetween, and a pair of source and drain regions interposing the channel region therebetween. The source and drain regions have portions in contact with the channel region, which portions are made of a specific semiconductor material that is wider in energy band gap than the channel region.
摘要翻译：提供了一种具有由碳纳米管（CNT）构成的沟道区，用于降低或最小化漏极漏电流的高性能半导体器件。除了CNT形成的沟道区域之外，该半导体器件还包括形成为覆盖沟道区域的栅电极，其间夹有栅极绝缘膜，并且在其间插入沟道区域的一对源极和漏极区域。源极区和漏极区具有与沟道区接触的部分，这些部分由能量带隙比通道区宽的特定半导体材料制成。

4. 发明授权

US07111029B2 Random number generating circuit 失效
公开(公告)号：US07111029B2
公开(公告)日：2006-09-19
申请号：US10235827
申请日：2002-09-06
申请人： Shinobu Fujita , Ken Uchida , Ryuji Ohba , Junji Koga
发明人： Shinobu Fujita , Ken Uchida , Ryuji Ohba , Junji Koga
IPC分类号： G06F1/02
CPC分类号： H04L9/0861 , G06F7/588
摘要： A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of “0” and “1” in the digital output values output from the uncertain logic circuit.

5. 发明授权

US06787795B2 Logic apparatus and logic circuit 有权
标题翻译：逻辑设备和逻辑电路
公开(公告)号：US06787795B2
公开(公告)日：2004-09-07
申请号：US09990362
申请日：2001-11-23
申请人： Ken Uchida , Junji Koga , Ryuji Ohba
发明人： Ken Uchida , Junji Koga , Ryuji Ohba
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L29/7888 , H01L49/006 , H03K19/08
摘要： A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between two tunnel barriers, which separate the conductive island from respective source/drain electrodes. A first charge storage region is insulatively disposed over and under the conductive island and a gate electrode, respectively. When charges are accumulated in the charge storage region, a Coulomb oscillation of the respective device is shifted by a half-period from the Coulomb oscillation that results when no charge has accumulated therein.
摘要翻译：具有串联或并联连接的第一和第二单电子器件的逻辑器件。每个单电子器件包括绝缘地设置在两个隧道势垒之间的导电岛，其将导电岛与相应的源/漏电极分离。第一电荷存储区分别绝缘地设置在导电岛和栅电极之上和之下。当在电荷存储区域中累积电荷时，各器件的库仑振荡从库仑振荡偏移了半周期，当没有电荷累积时产生库仑振荡。

6. 发明授权

US06680505B2 Semiconductor storage element 有权
标题翻译：半导体存储元件
公开(公告)号：US06680505B2
公开(公告)日：2004-01-20
申请号：US10107440
申请日：2002-03-28
申请人： Ryuji Ohba , Junji Koga , Ken Uchida
发明人： Ryuji Ohba , Junji Koga , Ken Uchida
IPC分类号： H01L2972
CPC分类号： G11C11/5671 , H01L21/28273 , H01L29/7883
摘要： A nonvolatile semiconductor storage element which has a charge stored layer as a floating gate, and whose storage time is made sufficiently long. The storage element comprises a channel region formed between a source region and a drain region; first and second tunnel insulator layers formed over the channel region and through which electrons can directly tunnel quantum-mechanically; and a conductive particle layer which is sandwiched in between the first and second tunnel insulator layers; the charge stored layer being formed on the second tunnel insulator layer. An energy level at which the information electron in the charge stored layer is injected is lower than the energy level of a conduction band edge in the channel region.
摘要翻译：一种具有电荷存储层作为浮动栅极并且其存储时间足够长的非易失性半导体存储元件。存储元件包括形成在源极区域和漏极区域之间的沟道区域; 形成在通道区域上的第一和第二隧道绝缘体层，电子可以通过其直接隧道量子力学; 以及夹在所述第一和第二隧道绝缘体层之间的导电性粒子层; 电荷存储层形成在第二隧道绝缘体层上。注入电荷存储层中的信息电子的能级低于沟道区的导带边缘的能级。

7. 发明授权

US07138651B2 Logic apparatus and logic circuit 有权
公开(公告)号：US07138651B2
公开(公告)日：2006-11-21
申请号：US10893916
申请日：2004-07-20
申请人： Ken Uchida , Junji Koga , Ryuji Ohba
发明人： Ken Uchida , Junji Koga , Ryuji Ohba
IPC分类号： H01L29/06
CPC分类号： B82Y10/00 , H01L29/7888 , H01L49/006 , H03K19/08
摘要： A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

8. 发明授权

US07737486B2 Non-volatile semiconductor storage device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US07737486B2
公开(公告)日：2010-06-15
申请号：US11859142
申请日：2007-09-21
申请人： Masumi Saitoh , Ken Uchida
发明人： Masumi Saitoh , Ken Uchida
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/165 , H01L29/7881
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变，并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

9. 发明授权

US5068267A Semiconductor device encapsulant consisting of epoxy resin composition 失效
标题翻译：环氧树脂组合物的半导体器件封装
公开(公告)号：US5068267A
公开(公告)日：1991-11-26
申请号：US405533
申请日：1989-09-12
申请人： Ken Uchida , Michiya Higashi , Naoko Kihara , Hiroshi Shimozawa , Akira Yoshizumo
发明人： Ken Uchida , Michiya Higashi , Naoko Kihara , Hiroshi Shimozawa , Akira Yoshizumo
IPC分类号： C08L61/06 , C08G59/00 , C08G59/32 , C08G59/62 , C08L61/04 , C08L63/00 , H01L23/29 , H01L23/31
CPC分类号： H01L23/293 , C08G59/3218 , C08L63/00 , H01L2924/0002
摘要： An encapsulant consisting of an epoxy resin composition and suitably used to encapsulate a semiconductor device which is to be surface-mounted contains(a) an epoxy resin,(b) a rubber-modified phenolic resin comprising a phenolic resin, and a methylmethacrylate-butadiene-styrene copolymer and a thermosetting silicon rubber dispersed in said phenolic resin,(c) a curing accelerator, and(d) a silica powder.

10. 发明授权

US4630086A Nonvolatile MNOS memory 失效
标题翻译：非易失性MNOS存储器
公开(公告)号：US4630086A
公开(公告)日：1986-12-16
申请号：US535233
申请日：1983-09-23
申请人： Nobuyuki Sato , Kyotake Uchiumi , Shinji Nabetani , Ken Uchida
发明人： Nobuyuki Sato , Kyotake Uchiumi , Shinji Nabetani , Ken Uchida
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/02 , H01L29/34
CPC分类号： G11C16/0433 , G11C16/0466 , H01L29/7883
摘要： A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.
摘要翻译：公开了一种非易失性存储器，其具有浮动型EEPROM和MNOS型EEPROM的优点，并且能够以低电压写入和擦除。非易失性存储器中的每个存储元件具有浮置栅极，控制栅极，半导体主体和浮置栅极之间的栅极绝缘膜，以及控制栅极和浮动栅极之间的层间绝缘膜。栅极绝缘膜由非常薄的SiO 2膜和形成在其上的薄的Si 3 N 4膜构成。注入用于存储数据的电荷的电荷重心位于浮动栅极内，而不在Si3N4膜内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式