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1. 发明授权

US4769787A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4769787A
公开(公告)日：1988-09-06
申请号：US888072
申请日：1986-07-22
申请人： Kazunori Furusawa , Shinji Nabetani , Yoshiaki Kamigaki , Masaaki Terasawa
发明人： Kazunori Furusawa , Shinji Nabetani , Yoshiaki Kamigaki , Masaaki Terasawa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C17/00 , G11C11/34
CPC分类号： G11C16/08 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14
摘要： Using a comparatively low supply voltage of, e.g., +5V and a minus gate voltage, the voltage difference between the gate of an MNOS transistor and a P-type well region in which a MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate can be fixed to a comparatively low potential, e.g., about +5V, so that a P-channel MOSFET formed on the semiconductor substrate operates with an ordinary signal level. Consequently, an EEPROM having peripheral circuits constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.
摘要翻译：使用例如+ 5V和负栅极电压的较低电源电压，MNOS晶体管的栅极与其中形成MNOS晶体管的P型阱区域之间的电压差相对变化，以执行写入和擦除MNOS晶体管。因此，N型半导体衬底的电位可以固定在比较低的电位，例如约+ 5V，使得形成在半导体衬底上的P沟道MOSFET以普通信号电平工作。因此，可以提供具有由CMOS电路构成的外围电路的EEPROM。因此，可以实现EEPROM的功耗的降低。

2. 发明授权

US5315547A Nonvolatile semiconductor memory device with selective tow erasure 失效
标题翻译：非易失性半导体存储器件，具有选择性擦除
公开(公告)号：US5315547A
公开(公告)日：1994-05-24
申请号：US960280
申请日：1992-10-13
申请人： Kazuyoshi Shoji , Tadashi Muto , Yasurou Kubota , Koichi Seki , Kazuto Izawa , Shinji Nabetani, deceased
发明人： Kazuyoshi Shoji , Tadashi Muto , Yasurou Kubota , Koichi Seki , Kazuto Izawa , Shinji Nabetani, deceased
IPC分类号： G11C16/12 , G11C16/16 , G11C16/30 , G11C7/00
CPC分类号： G11C16/30 , G11C16/12 , G11C16/16
摘要： In a nonvolatile semiconductor memory device, a high voltage is selectively exerted between a word line to which the control gates of nonvolatile semiconductor memory elements are coupled and a source line to which the sources of the nonvolatile semiconductor memory elements are coupled, whereby charges stored in the floating gates are extracted through the source line. In addition, the nonvolatile semiconductor memory elements to be erased are provided with a source potential having ramp-rate characteristics such that the sources are gradually raised from a low voltage to the high voltage. Thus, the erasure of a predetermined part of the memory array of the memory device becomes possible in accordance with the division of the source lines or that of the word lines, and an excessive intense electric field can be prevented from acting between the floating gates and the sources because a ramp rate is used for the erasing high voltage.
摘要翻译：在非易失性半导体存储器件中，高电压选择性地施加在与非易失性半导体存储元件的控制栅极耦合的字线和非易失性半导体存储元件的源耦合到的源极线之间，由此存储在浮动栅极通过源极线提取。另外，要被擦除的非易失性半导体存储元件被提供有具有斜率特性的源极电位，使得源极从低电压逐渐升高到高电压。因此，根据源极线或字线的划分，存储器件的存储器阵列的预定部分的擦除成为可能，并且可以防止过大的强电场作用在浮动栅极和因为使用斜坡率来消除高电压。

3. 发明授权

US5012445A Programmable read only memory being capable of controlling internal writing voltage of external voltage 失效
标题翻译：可编程只读存储器能够控制外部电压的内部写入电压
公开(公告)号：US5012445A
公开(公告)日：1991-04-30
申请号：US225314
申请日：1988-07-28
申请人： Ujiie Kazuaki , Shinji Nabetani
发明人： Ujiie Kazuaki , Shinji Nabetani
IPC分类号： G11C11/14 , G11C5/14 , G11C16/12 , G11C16/30 , G11C17/18
CPC分类号： G11C16/12 , G11C16/30 , G11C17/18 , G11C5/145
摘要： A semiconductor integrated circuit device enabled to perform both a normal writing operation using a voltage elevated with the internal supply voltage taken as the reference voltage and a writing operation with the use of another voltage elevated with an external voltage applied to an external terminal taken as the reference voltage, whereby margin measurement, high-voltage test, and accelerated test are enabled to be performed even after packaging. Further, by providing the apparatus with a mode selector having a plurality of latch circuits operating at different timing connected to an input terminal so that modes are switched by changing combination of the signals latched in such latch circuits, the number of operating modes can be increased without increasing the number of pins.
摘要翻译：一种半导体集成电路器件，其能够使用以内部电源电压为参考电压升高的电压进行正常写入操作，并且使用另外的电压进行写入操作，该另一个电压通过施加到外部端子的外部电压而升高参考电压，即使在包装之后也能够进行余量测量，高压测试和加速测试。此外，通过为装置提供具有多个锁存电路的模式选择器，该多个锁存电路以与连接到输入端子的不同的定时工作，以便通过改变锁存在这种锁存电路中的信号的组合来切换模式，可以增加操作模式的数量而不增加引脚数。

4. 发明授权

US4692904A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4692904A
公开(公告)日：1987-09-08
申请号：US737882
申请日：1985-05-28
申请人： Nobuyuki Sato , Kazuaki Ujiie , Masaaki Terasawa , Shinji Nabetani
发明人： Nobuyuki Sato , Kazuaki Ujiie , Masaaki Terasawa , Shinji Nabetani
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/20 , G11C16/22 , G11C16/30 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/225 , G11C16/20 , G11C16/30
摘要： A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into the semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an erroneous operation from developing when the power source is closed, provision is made of a power source closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is being applied to the memory element from the time from when the power source circuit is closed up to the times when the read operation mode is designated by an external control signal.
摘要翻译：半导体集成电路器件包括半导体非易失性存储器，产生将数据写入半导体非易失性存储器所需的高电压的升压电路和控制电路。然而，利用如此构造的装置，当电源关闭时，各种外部控制信号通常不能承担确定的电平。如果由于外部控制信号的不清楚而将指定的操作模式错误地确定为写入操作模式，则写入操作被错误地执行。为了防止在电源闭合时发生这种错误的操作，提供电源闭合检测器电路和合适的门电路。由于这些电路，从电源电路闭合直到由外部控制信号指定读取操作模式的时刻，升压电路的输出被施加到存储元件。

5. 发明授权

US4881201A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4881201A
公开(公告)日：1989-11-14
申请号：US78764
申请日：1987-07-28
申请人： Nobuyuki Sato , Kazuaki Ujiie , Masaaki Terasawa , Shinji Nabetani
发明人： Nobuyuki Sato , Kazuaki Ujiie , Masaaki Terasawa , Shinji Nabetani
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/20 , G11C16/22 , G11C16/30 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L29/788 , H01L29/792
CPC分类号： G11C16/225 , G11C16/20 , G11C16/30
摘要： A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into said semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an eronneous operation from developing when the power source is closed, provision is made of a power souce closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is prevented from being applied to the memory element from the time from when the power source circuit is closed up to the time when the read operation mode is designated by an external control signal.
摘要翻译：半导体集成电路器件包括半导体非易失性存储器，产生将数据写入所述半导体非易失性存储器所需的高电压的升压电路以及控制电路。然而，利用如此构造的装置，当电源关闭时，各种外部控制信号通常不能承担确定的电平。如果由于外部控制信号的不清楚而将指定的操作模式错误地确定为写入操作模式，则写入操作被错误地执行。为了防止在电源关闭时发生这种恶意操作，请提供电源闭合检测器电路和合适的门电路。由于这些电路，从电源电路闭合直到由外部控制信号指定读取操作模式的时间，防止升压电路的输出被施加到存储元件。

6. 发明授权

US4630086A Nonvolatile MNOS memory 失效
标题翻译：非易失性MNOS存储器
公开(公告)号：US4630086A
公开(公告)日：1986-12-16
申请号：US535233
申请日：1983-09-23
申请人： Nobuyuki Sato , Kyotake Uchiumi , Shinji Nabetani , Ken Uchida
发明人： Nobuyuki Sato , Kyotake Uchiumi , Shinji Nabetani , Ken Uchida
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/02 , H01L29/34
CPC分类号： G11C16/0433 , G11C16/0466 , H01L29/7883
摘要： A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.
摘要翻译：公开了一种非易失性存储器，其具有浮动型EEPROM和MNOS型EEPROM的优点，并且能够以低电压写入和擦除。非易失性存储器中的每个存储元件具有浮置栅极，控制栅极，半导体主体和浮置栅极之间的栅极绝缘膜，以及控制栅极和浮动栅极之间的层间绝缘膜。栅极绝缘膜由非常薄的SiO 2膜和形成在其上的薄的Si 3 N 4膜构成。注入用于存储数据的电荷的电荷重心位于浮动栅极内，而不在Si3N4膜内。

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