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1. 发明授权

US06690030B2 Semiconductor device with negative differential resistance characteristics 失效
标题翻译：具有负差分电阻特性的半导体器件
公开(公告)号：US06690030B2
公开(公告)日：2004-02-10
申请号：US09798923
申请日：2001-03-06
申请人： Junji Koga , Ken Uchida , Ryuji Ohba , Akira Toriumi
发明人： Junji Koga , Ken Uchida , Ryuji Ohba , Akira Toriumi
IPC分类号： H01L2940
CPC分类号： H01L27/1104 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/511 , H01L29/7881
摘要： A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load. The negative differential resistance and the load are serially connected together between a low-voltage power supply (ground potential) Vss and a high-voltage power supply Vdd, thus enabling forming a transistor with a built-in bistable circuit. Potential information of the first polysilicon film for use as a data storage node is read with a transistor amplification applied thereto. Thus, data read is performed at high speeds. Simultaneously, a current flowing between the power supplies is suppressed to a lower level, thereby minimizing power consumption in wait modes.
摘要翻译：形成在硅衬底表面上的栅极氧化膜的厚度部分地减小或者在其源区域上的指定部分“薄化”。在栅极区域中，以层叠的顺序形成包括p型导电体的第一多晶硅或“多晶硅”膜，隧道氧化物膜和第二p型多晶硅膜的多层结构。源极区域和第一多晶硅膜构成了高浓度杂质掺杂的pn结，其间铺设有薄的氧化硅膜，提供了也称为Esaki二极管的隧道二极管。二极管用于负差分电阻。此外，第一和第二多晶硅膜之间的部分是用作负载的非线性隧道电阻器。负的差分电阻和负载在低压电源（接地电位）Vss和高压电源Vdd之间串联连接在一起，从而能够形成具有内置双稳态电路的晶体管。读取用作数据存储节点的第一多晶硅膜的电位信息，并施加晶体管放大。因此，高速执行数据读取。同时，在电源之间流动的电流被抑制到较低的电平，从而使等待模式中的功耗最小化。

2. 发明授权

US6060748A Semiconductor integrated circuit device using a silicon-on-insulator substrate 失效
标题翻译：使用绝缘体上硅衬底的半导体集成电路器件
公开(公告)号：US6060748A
公开(公告)日：2000-05-09
申请号：US997508
申请日：1997-12-23
申请人： Ken Uchida , Akira Toriumi , Akiko Ohata , Junji Koga
发明人： Ken Uchida , Akira Toriumi , Akiko Ohata , Junji Koga
IPC分类号： H01L21/84 , H01L23/528 , H01L27/12 , H01L25/00 , H01L29/00
CPC分类号： H01L23/5286 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor integrated circuit (IC) device has a silicon-on-insulator substrate having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a silicon layer formed on the insulating film. The semiconductor IC device includes at least one semiconductor device formed on the semiconductor substrate, and at least one semiconductor device formed on the silicon layer and operated with a power-supply voltage different from a power-supply voltage for the semiconductor device formed on the semiconductor substrate.
摘要翻译：半导体集成电路（IC）器件具有绝缘体上硅衬底，其具有半导体衬底，形成在半导体衬底上的绝缘膜和形成在绝缘膜上的硅层。半导体IC器件包括形成在半导体衬底上的至少一个半导体器件和形成在硅层上的至少一个半导体器件，并且以形成在半导体上的半导体器件的电源电压不同的电源电压来操作基质。

3. 发明申请

US20100019357A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100019357A1
公开(公告)日：2010-01-28
申请号：US11574483
申请日：2005-08-30
申请人： Akira Toriumi , Koji Kita , Kazuyuki Tomida , Yoshiki Yamamoto
发明人： Akira Toriumi , Koji Kita , Kazuyuki Tomida , Yoshiki Yamamoto
IPC分类号： H01L29/51 , H01L21/314
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/31604 , H01L21/31645
摘要： A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVB) semiconductor board and a first oxide layer. The first oxide layer is composed of MO2 existing on the board, where M is a first metal species selected from the group 4 (IVA); and M′xOy, where M′ is a second metal species selected from the group 3 (IIIA) and a group composed of lanthanide series, and x and y are integers decided by the oxidation number of M.
摘要翻译：提供具有高介电常数的栅极绝缘膜，设置有栅极绝缘膜的半导体器件及其制造方法。半导体器件具有第14族（IVB）半导体基板和第1氧化物层。第一氧化物层由存在于板上的MO2组成，其中M是选自第4族（IVA）的第一种金属; 和M'xOy，其中M'是选自组3（IIIA）的第二种金属和由镧系元素组成的组，x和y是由氧化数M决定的整数。

4. 发明授权

US07102203B2 Semiconductor device including field-effect transistor 失效
标题翻译：半导体器件包括场效应晶体管
公开(公告)号：US07102203B2
公开(公告)日：2006-09-05
申请号：US10806276
申请日：2004-03-23
申请人： Hideaki Fujiwara , Akira Toriumi
发明人： Hideaki Fujiwara , Akira Toriumi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L21/336
CPC分类号： H01L29/78696 , H01L21/28194 , H01L29/458 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/66621 , H01L29/66772 , H01L29/78618 , H01L29/78621 , H01L29/78636
摘要： A semiconductor device capable of inhibiting a threshold voltage from increase also when employing a gate electrode consisting of a metal is provided. This semiconductor device comprises a pair of source/drain regions lifted up in an elevated structure, a gate insulator film, formed on a channel region, consisting of a high dielectric constant insulator film having a dielectric constant larger than 3.9 and a gate electrode including a first metal layer coming into contact with the gate insulator film and having a work function controlled to have a Fermi level around the energy level of a band gap end of silicon constituting the source/drain regions.
摘要翻译：提供了当采用由金属组成的栅电极时能够抑制阈值电压增加的半导体器件。该半导体器件包括以升高的结构提升的一对源极/漏极区域，形成在沟道区域上的栅极绝缘膜，其由介电常数大于3.9的高介电常数绝缘膜和包括第一金属层与栅极绝缘膜接触并且具有控制成在构成源极/漏极区域的硅的带隙端的能级周围具有费米能级的功函数。

5. 发明授权

US06208002B1 Field effect transistor and manufacturing method thereof 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US06208002B1
公开(公告)日：2001-03-27
申请号：US09229567
申请日：1999-01-13
申请人： Hideki Satake , Akira Toriumi
发明人： Hideki Satake , Akira Toriumi
IPC分类号： H01L31119
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/3003 , H01L29/518
摘要： In the manufacturing process of a field effect transistor, the main surface of the semiconductor layer is exposed to the atmosphere containing oxygen atoms and nitrogen atoms at first. Then, the gate insulating film is formed by introducing heavy hydrogen atoms therein such that the concentration of heavy hydrogen atoms in the interface of a gate insulating film and the gate electrode is higher than that of a middle portion of the gate insulating film located in the middle of the gate insulating film in the direction of the thickness of the gate insulating film. Subsequently, the gate electrode is formed on the gate insulating film. Then, source and drain regions are formed on the main surface of the semiconductor layer to sandwich the gate electrode therebetween. By virtue of the above-mentioned method, a gate insulating film having a small thickness and high electric stability can be obtained.
摘要翻译：在场效晶体管的制造过程中，首先将半导体层的主表面暴露于含有氧原子和氮原子的气氛中。然后，通过在其中引入重氢原子形成栅极绝缘膜，使得栅极绝缘膜和栅电极的界面中的重氢原子的浓度高于位于栅极绝缘膜中的栅极绝缘膜的中间部分栅极绝缘膜的中间在栅极绝缘膜的厚度方向上。随后，在栅极绝缘膜上形成栅电极。然后，在半导体层的主表面上形成源极和漏极区，以将栅电极夹在其间。通过上述方法，可以获得厚度小，电稳定性高的栅极绝缘膜。

6. 发明申请

US20090173998A1 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US20090173998A1
公开(公告)日：2009-07-09
申请号：US12320988
申请日：2009-02-10
申请人： Nobuyuki Mise , Akira Toriumi
发明人： Nobuyuki Mise , Akira Toriumi
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/28194 , H01L21/28202 , H01L29/495 , H01L29/4975 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66795 , H01L29/7833
摘要： In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.

7. 发明授权

US07397094B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07397094B2
公开(公告)日：2008-07-08
申请号：US11114195
申请日：2005-04-26
申请人： Toshihide Nabatame , Akira Toriumi , Tsuyoshi Horikawa , Kunihiko Iwamoto , Koji Tominaga
发明人： Toshihide Nabatame , Akira Toriumi , Tsuyoshi Horikawa , Kunihiko Iwamoto , Koji Tominaga
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/823857 , H01L29/513 , H01L29/7833
摘要： To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.
摘要翻译：为了提供能够抑制MISFET的栅极绝缘膜的缺陷密度的半导体器件，获得足够的电特性，并使栅极绝缘膜的等效氧化物厚度（EOT）为1.0nm以下。 MISFET形成为具有形成在硅衬底的主表面上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极，其中栅极绝缘膜包括由金属氧化物层形成的金属硅酸盐层和硅氧化物层和金属硅酸盐层形成为具有从硅衬底侧到栅电极侧的金属和硅的浓度梯度。

8. 发明申请

US20060278937A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20060278937A1
公开(公告)日：2006-12-14
申请号：US11448110
申请日：2006-06-07
申请人： Masaru Kadoshima , Toshihide Nabatame , Akira Toriumi
发明人： Masaru Kadoshima , Toshihide Nabatame , Akira Toriumi
IPC分类号： H01L29/76
CPC分类号： H01L23/485 , H01L21/823835 , H01L21/823842 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： As shown in FIG. 2B, a gate electrode is formed on a gate insulating film on a semiconductor substrate. A high dielectric film with a dielectric constant higher than that of a silicon oxide film is used for the gate insulating film, and a platinum-rich silicide film is used for the gate electrode. The platinum-rich silicide film indicates a film with a ratio of silicon atoms to platinum atoms of less than 1 (PtSix: x
摘要翻译：如图所示。如图2B所示，在半导体衬底上的栅极绝缘膜上形成栅电极。对于栅极绝缘膜使用介电常数高于氧化硅膜的高电介质膜，并且将富铂的硅化物膜用于栅电极。富含铂的硅化物膜表示硅原子与铂原子的比率小于1（PtSix：x <1）的膜。作为导电杂质的硼被引入到由富铂的硅化物膜构成的栅电极中，并且硼在栅极绝缘膜和栅电极之间的界面处分离。

9. 发明申请

US20060071282A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060071282A1
公开(公告)日：2006-04-06
申请号：US11242909
申请日：2005-10-05
申请人： Masaru Kadoshima , Toshihide Nabatame , Akira Toriumi
发明人： Masaru Kadoshima , Toshihide Nabatame , Akira Toriumi
IPC分类号： H01L29/94
CPC分类号： H01L29/517 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/4975 , H01L29/66545
摘要： A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of a n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide film. Also, the gate electrode is composed of a Pt silicide film with a ratio of Si atoms to Pt atoms of approximately 1 (PtSix: x=1) in the vicinity of a region in contact with the gate insulator. Also, the gate electrode of the p channel MIS transistor is composed of a Pt silicide film with a ratio of Si atoms to Pt atoms of less than 1 (PtSix: x
摘要翻译：提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪膜组成。此外，栅电极由与栅极接触的区域附近的Si原子与Pt原子的比率为约1（PtSi x x：x = 1）的Pt硅化物膜构成绝缘子。此外，p沟道MIS晶体管的栅电极由Si原子与Pt原子的比例小于1（PtSi x x：x <1）的Pt硅化物膜组成，与栅极绝缘体接触的区域。因此，抑制了栅电极的费米能级钉扎。

10. 发明授权

US6111288A Quantum tunneling effect device and semiconductor composite substrate 失效
标题翻译：量子隧道效应器件和半导体复合衬底
公开(公告)号：US6111288A
公开(公告)日：2000-08-29
申请号：US42610
申请日：1998-03-17
申请人： Hiroshi Watanabe , Naoki Yasuda , Akira Toriumi , Tomoharu Tanaka , Toru Tanzawa
发明人： Hiroshi Watanabe , Naoki Yasuda , Akira Toriumi , Tomoharu Tanaka , Toru Tanzawa
IPC分类号： H01L29/06 , H01L27/115 , H01L27/146 , H01L29/66 , H01L29/76 , H01L29/772 , H01L29/78 , H01L29/788 , H01L31/0232
CPC分类号： H01L31/0232 , H01L27/115 , H01L27/146 , H01L29/7606 , H01L29/772 , H01L29/7883
摘要： A new switching element and a circuit device and the like using the same element are provided, which comprises semiconductor in which a channel region is formed at an interface with an insulating film, first and second terminals S, D, which are located in corresponding manner to both ends of the channel region, and through which a tunnel current is let to flow into the channel region, and a third terminal G giving a high frequency vibration to a potential barrier of the channel region through the insulating film, wherein the tunnel current flowing into the channel region is increased as a value of an exponential function is increased with a predetermined threshold vibration frequency as a boundary value.
摘要翻译：提供了使用相同元件的新的开关元件和电路器件等，其包括半导体，其中在与绝缘膜的界面处形成沟道区域，第一和第二端子S，D以相应的方式定位到通道区域的两端，隧道电流通过其流入沟道区域，以及通过绝缘膜向通道区域的势垒施加高频振动的第三端子G，其中隧道电流随着指数函数的值以预定阈值振动频率作为边界值增加，流入通道区域的流量增加。

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