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1. 发明授权

US06974995B1 Method and system for forming dual gate structures in a nonvolatile memory using a protective layer 失效
标题翻译：使用保护层在非易失性存储器中形成双栅极结构的方法和系统
公开(公告)号：US06974995B1
公开(公告)日：2005-12-13
申请号：US10032757
申请日：2001-12-27
申请人： Angela Hui , Shenqing Fang , Hiroyuki Kinoshita , Kelwin Ko , Wenmei Li , Yu Sun , Hiroyuki Ogawa , Chi Chang
发明人： Angela Hui , Shenqing Fang , Hiroyuki Kinoshita , Kelwin Ko , Wenmei Li , Yu Sun , Hiroyuki Ogawa , Chi Chang
IPC分类号： H01L21/8238 , H01L21/8239 , H01L27/105 , H01L29/772
CPC分类号： H01L21/823842 , H01L27/1052
摘要： A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.
摘要翻译：描述了一种用于提供半导体器件的方法和系统。半导体包括芯和外围。所述方法和系统包括在芯中提供多个核心堆栈，在核心中提供多个源极和在周边的多个外围栅极叠层。多个核心栅堆叠中的每一个包括第一多晶硅栅极和位于第一多晶硅栅极上方的WSi层。多个源位于多个核心栅极叠层的一部分之间。多个外围栅极堆叠中的每一个在第二多晶硅栅极上包括第二多晶硅栅极和CoSi层。

2. 发明授权

US06806155B1 Method and system for scaling nonvolatile memory cells 有权
标题翻译：用于缩放非易失性存储单元的方法和系统
公开(公告)号：US06806155B1
公开(公告)日：2004-10-19
申请号：US10150255
申请日：2002-05-15
申请人： Kelwin Ko , Chi Chang
发明人： Kelwin Ko , Chi Chang
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468
摘要： A method and system for providing a semiconductor device are described. The method and system include providing a plurality of gate stacks and a first source drain halo implant. The first source and drain halo implant uses the plurality of gate stacks as a mask. The method and system also include providing a lightly doped source and drain implant and a N+ source and drain implant. The source connection implant is for connecting a portion of the plurality of sources. The second source and drain implant uses the plurality of gate stacks as a mask. Moreover, CoSi formed on the source region provides a lower resistence for lines connecting the sources, allowing a lower dose to be used for the N+ source and drain implant.
摘要翻译：描述了一种用于提供半导体器件的方法和系统。该方法和系统包括提供多个栅极堆叠和第一源极漏极注入。第一源极和漏极晕轮植入物使用多个栅极堆叠作为掩模。该方法和系统还包括提供轻掺杂的源极和漏极注入以及N +源极和漏极植入物。源连接植入物用于连接多个源的一部分。第二源极和漏极注入使用多个栅极叠层作为掩模。此外，形成在源极区上的CoSi对连接源的线路提供较低的电阻，允许较低剂量用于N +源极和漏极植入物。

3. 发明授权

US09106734B2 Computer system and processor having integrated phone functionality 有权
标题翻译：具有集成手机功能的计算机系统和处理器
公开(公告)号：US09106734B2
公开(公告)日：2015-08-11
申请号：US13584527
申请日：2012-08-13
申请人： Chi Chang
发明人： Chi Chang
IPC分类号： H04M11/00 , H04M1/247 , G06F3/02 , G06F3/023 , G06F3/0489
CPC分类号： H04M1/2473 , G06F3/021 , G06F3/023 , G06F3/0489
摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.
摘要翻译：包括电话功能的计算机系统。计算机系统包括第一键盘和第一显示器。计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。计算机系统可以在第一模式，第二模式或第三模式中操作。在第一模式中，只有电话部分被激活，并且电话部分提供放置和接收电话呼叫的功能，而不从计算机系统移除。在第二模式中，处理器的电话部分和第一功能单元被激活。在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

4. 发明授权

US08455268B2 Gate replacement with top oxide regrowth for the top oxide improvement 有权
标题翻译：门顶置换，顶部氧化物再生长，用于顶部氧化物改良
公开(公告)号：US08455268B2
公开(公告)日：2013-06-04
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

5. 发明授权

US07915123B1 Dual charge storage node memory device and methods for fabricating such device 有权
标题翻译：双电荷存储节点存储器件及其制造方法
公开(公告)号：US07915123B1
公开(公告)日：2011-03-29
申请号：US11408866
申请日：2006-04-20
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Kyunghoon Min , Chi Chang
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Kyunghoon Min , Chi Chang
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792 , Y10S438/954
摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.
摘要翻译：提供了一种双节点存储器件及其制造方法。在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

6. 发明授权

US07671403B2 P-channel NAND in isolated N-well 有权
标题翻译：隔离N阱中的P沟道NAND
公开(公告)号：US07671403B2
公开(公告)日：2010-03-02
申请号：US11567257
申请日：2006-12-06
申请人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
发明人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.
摘要翻译：一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质。所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第基质。

7. 发明授权

US07616722B2 Method and circuitry for extracting clock in clock data recovery system 有权
标题翻译：在时钟数据恢复系统中提取时钟的方法和电路
公开(公告)号：US07616722B2
公开(公告)日：2009-11-10
申请号：US11148852
申请日：2005-06-08
申请人： Chi Chang , Shuyu Lin
发明人： Chi Chang , Shuyu Lin
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.
摘要翻译：提供了一种在时钟数据恢复系统中提取时钟的方法。该方法包括以下步骤。首先，对多个串行链路发送数据进行采样，生成多个脉冲信号并依次排列。然后，在产生所有脉冲信号之后插入一个标记，并将其延迟预定的延迟时间。预定的延迟时间小于两个相邻脉冲信号之间的周期，并且两个相邻脉冲信号之间的周期被划分为两个子周期预定的延迟时间。然后，检查每个子周期中的数据状态是否改变，并且该操作重复预定次数。最后，当生成在预定次数内没有数据状态改变的脉冲信号时，提取时钟。

8. 发明申请

US20080142875A1 Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes 有权
标题翻译：具有分离电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法
公开(公告)号：US20080142875A1
公开(公告)日：2008-06-19
申请号：US11639666
申请日：2006-12-15
申请人： Chungho Lee , Wei Zheng , Chi Chang , Unsoon Kim , Hiroyuki Kinoshita
发明人： Chungho Lee , Wei Zheng , Chi Chang , Unsoon Kim , Hiroyuki Kinoshita
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/1037 , H01L29/1083 , H01L29/42332 , H01L29/42348 , H01L29/66537 , H01L29/7887 , H01L29/7923
摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.
摘要翻译：公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件第二元件的侧壁。形成与第一存储元件和第二存储元件接触的字线。

9. 发明申请

US20080135918A1 P-CHANNEL NAND IN ISOLATED N-WELL 有权
标题翻译： P-CHANNEL NAND在隔离N-WELL中
公开(公告)号：US20080135918A1
公开(公告)日：2008-06-12
申请号：US11567257
申请日：2006-12-06
申请人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
发明人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568
摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.
摘要翻译：一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质。所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第基质。

10. 发明申请

US20080064165A1 DUAL STORAGE NODE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：双存储节点存储器件及其制造方法
公开(公告)号：US20080064165A1
公开(公告)日：2008-03-13
申请号：US11530145
申请日：2006-09-08
申请人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
发明人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/7923
摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.
摘要翻译：已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。层状结构包括隧道介电层和电荷存储层。位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

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