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1. 发明授权

US06974995B1 Method and system for forming dual gate structures in a nonvolatile memory using a protective layer 失效
标题翻译：使用保护层在非易失性存储器中形成双栅极结构的方法和系统
公开(公告)号：US06974995B1
公开(公告)日：2005-12-13
申请号：US10032757
申请日：2001-12-27
申请人： Angela Hui , Shenqing Fang , Hiroyuki Kinoshita , Kelwin Ko , Wenmei Li , Yu Sun , Hiroyuki Ogawa , Chi Chang
发明人： Angela Hui , Shenqing Fang , Hiroyuki Kinoshita , Kelwin Ko , Wenmei Li , Yu Sun , Hiroyuki Ogawa , Chi Chang
IPC分类号： H01L21/8238 , H01L21/8239 , H01L27/105 , H01L29/772
CPC分类号： H01L21/823842 , H01L27/1052
摘要： A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.
摘要翻译：描述了一种用于提供半导体器件的方法和系统。半导体包括芯和外围。所述方法和系统包括在芯中提供多个核心堆栈，在核心中提供多个源极和在周边的多个外围栅极叠层。多个核心栅堆叠中的每一个包括第一多晶硅栅极和位于第一多晶硅栅极上方的WSi层。多个源位于多个核心栅极叠层的一部分之间。多个外围栅极堆叠中的每一个在第二多晶硅栅极上包括第二多晶硅栅极和CoSi层。

2. 发明授权

US06808992B1 Method and system for tailoring core and periphery cells in a nonvolatile memory 有权
标题翻译：用于定制非易失性存储器中的核心和外围单元的方法和系统
公开(公告)号：US06808992B1
公开(公告)日：2004-10-26
申请号：US10150240
申请日：2002-05-15
申请人： Kelwin Ko , Shenqing Fang , Angela T. Hui , Hiroyuki Kinoshita , Wenmei Li , Yu Sun , Hiroyuki Ogawa
发明人： Kelwin Ko , Shenqing Fang , Angela T. Hui , Hiroyuki Kinoshita , Wenmei Li , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536 , H01L29/6656
摘要： A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.
摘要翻译：描述了一种用于提供半导体器件的方法和系统。半导体器件包括衬底，芯和周边。芯包括具有第一多个边缘的多个核心栅极叠层，而周边具有多个具有第二多个边缘的外围栅极堆叠。该方法和系统包括提供多个芯间隔件，多个外围间隔件，多个芯源和多个导电区域。芯间隔件位于第一多个边缘处并且具有厚度。外围间隔件位于第二多个边缘处并且具有大于第一厚度的第二厚度。核心源位于多个核心门堆栈之间。导电区域在多个核心源上。该方法允许不同厚度的间隔件形成在芯部和周边中，使得间隔件可以根据芯部和周边的不同要求进行调整。

3. 发明申请

US20050164450A1 Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元的低Vss电阻和二极管的结构和方法
公开(公告)号：US20050164450A1
公开(公告)日：2005-07-28
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L29/417 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

4. 发明授权

US07301193B2 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元中低Vss电阻和减少DIBL的结构和方法
公开(公告)号：US07301193B2
公开(公告)日：2007-11-27
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

5. 发明授权

US06583009B1 Innovative narrow gate formation for floating gate flash technology 有权
标题翻译：用于浮栅闪存技术的创新窄门形成
公开(公告)号：US06583009B1
公开(公告)日：2003-06-24
申请号：US10178106
申请日：2002-06-24
申请人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
发明人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/952
摘要： The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.
摘要翻译：本发明涉及一种形成层叠栅极闪存单元的方法，包括在半导体衬底上连续形成隧道氧化物层，第一导电层，多晶硅间介质层和第二导电层。该方法还包括在第二导电层上形成牺牲层，以及图案化牺牲层以形成具有与其相关联的至少一个侧向侧壁边缘的牺牲层特征。然后在牺牲层的横向侧壁边缘上形成侧壁间隔物，其中间隔件具有与其相关联的宽度，并且去除图案化的牺牲层特征。最后，使用间隔物作为硬掩模来图案化第二导电层，多晶硅间电介质和第一导电层，并且限定堆叠栅极，其中堆叠栅极的宽度是间隔物宽度的函数。

6. 发明授权

US06806155B1 Method and system for scaling nonvolatile memory cells 有权
标题翻译：用于缩放非易失性存储单元的方法和系统
公开(公告)号：US06806155B1
公开(公告)日：2004-10-19
申请号：US10150255
申请日：2002-05-15
申请人： Kelwin Ko , Chi Chang
发明人： Kelwin Ko , Chi Chang
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468
摘要： A method and system for providing a semiconductor device are described. The method and system include providing a plurality of gate stacks and a first source drain halo implant. The first source and drain halo implant uses the plurality of gate stacks as a mask. The method and system also include providing a lightly doped source and drain implant and a N+ source and drain implant. The source connection implant is for connecting a portion of the plurality of sources. The second source and drain implant uses the plurality of gate stacks as a mask. Moreover, CoSi formed on the source region provides a lower resistence for lines connecting the sources, allowing a lower dose to be used for the N+ source and drain implant.
摘要翻译：描述了一种用于提供半导体器件的方法和系统。该方法和系统包括提供多个栅极堆叠和第一源极漏极注入。第一源极和漏极晕轮植入物使用多个栅极堆叠作为掩模。该方法和系统还包括提供轻掺杂的源极和漏极注入以及N +源极和漏极植入物。源连接植入物用于连接多个源的一部分。第二源极和漏极注入使用多个栅极叠层作为掩模。此外，形成在源极区上的CoSi对连接源的线路提供较低的电阻，允许较低剂量用于N +源极和漏极植入物。

7. 发明授权

US07071101B1 Sacrificial TiN arc layer for increased pad etch throughput 有权
标题翻译：牺牲TiN电弧层，用于增加焊盘蚀刻吞吐量
公开(公告)号：US07071101B1
公开(公告)日：2006-07-04
申请号：US09208325
申请日：1998-12-09
申请人： Jeffrey A. Shields , Kelwin Ko
发明人： Jeffrey A. Shields , Kelwin Ko
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31138 , H01L21/32136
摘要： A method of manufacturing a semiconductor device wherein a final layer of metal is formed on a layer of interlayer dielectric, forming a layer of TiN on the final layer of metal, forming a layer of photoresist on the layer of TiN, patterning and developing the layer of photoresist exposing portions of the final metal layer, and etching the exposed portions of the final metal layer forming metal structures. The layer of photoresist and layer of TiN are removed. A blanket layer of interlayer dielectric is formed on the surface of the semiconductor device. A second layer of photoresist is formed on the blanket layer of interlayer dielectric. The second layer of photoresist is patterned and developed exposing portions of the interlayer dielectric overlying the metal structures. The exposed portions of the interlayer dielectric are etched down to the surface of the metal structures.
摘要翻译：一种制造半导体器件的方法，其中在层间电介质层上形成最终的金属层，在金属的最终层上形成TiN层，在TiN层上形成光致抗蚀剂层，图案化和显影层的光致抗蚀剂暴露最终金属层的部分，并蚀刻最终金属层形成金属结构的暴露部分。去除光致抗蚀剂层和TiN层。在半导体器件的表面上形成层间绝缘层的覆盖层。在层间电介质的覆盖层上形成第二层光致抗蚀剂。将第二层光致抗蚀剂图案化和显影，使覆盖金属结构的层间电介质的部分暴露。层间电介质的暴露部分被蚀刻到金属结构的表面。

8. 发明授权

US6143608A Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation 有权
标题翻译：阻挡层在隧道氧化物氮化期间减少外围栅极区域的氮污染
公开(公告)号：US6143608A
公开(公告)日：2000-11-07
申请号：US283308
申请日：1999-03-31
申请人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
发明人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.
摘要翻译：本发明描述了在半导体芯片的周边区域中制造栅极氧化物区域的方法，其中栅极氧化物区域具有改善的电性能。所述方法包括在半导体芯片的周边上沉积阻挡层，以防止在半导体芯片的芯区域中的氮化步骤期间将杂质氮原子引入周围。通过防止周围的栅极区域的污染，如此产生的栅极氧化物区域具有增加的击穿电压和增加的可靠性。本发明描述了用于蚀刻用于保护周边免受隧道氧化物氮化的阻挡层的方法。用本发明的方法制造的半导体器件具有更长的预期寿命，并且可以以较高的器件密度制造。

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