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1. 发明申请

US20110143462A1 ADJUSTING SUBSTRATE TEMPERATURE TO IMPROVE CD UNIFORMITY 有权
标题翻译：调整基板温度以提高光盘的均匀性
公开(公告)号：US20110143462A1
公开(公告)日：2011-06-16
申请号：US12966506
申请日：2010-12-13
申请人： Keith William Gaff , Harmeet Singh , Keith Comendant , Vahid Vahedi
发明人： Keith William Gaff , Harmeet Singh , Keith Comendant , Vahid Vahedi
IPC分类号： H01L21/3065 , H01L21/66
CPC分类号： H01J37/20 , H01L21/67248 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.
摘要翻译：一种等离子体蚀刻系统，具有具有多个可独立控制的加热器区域的基板支撑组件。等离子体蚀刻系统被配置为控制预定位置的蚀刻温度，从而可以补偿临界器件参数的预蚀刻和/或蚀刻后不均匀性。

2. 发明授权

US08642480B2 Adjusting substrate temperature to improve CD uniformity 有权
标题翻译：调整基板温度以提高CD均匀性
公开(公告)号：US08642480B2
公开(公告)日：2014-02-04
申请号：US12966506
申请日：2010-12-13
申请人： Keith William Gaff , Harmeet Singh , Keith Comendant , Vahid Vahedi
发明人： Keith William Gaff , Harmeet Singh , Keith Comendant , Vahid Vahedi
IPC分类号： H01L21/66 , H01L21/3065
CPC分类号： H01J37/20 , H01L21/67248 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.
摘要翻译：一种等离子体蚀刻系统，具有具有多个可独立控制的加热器区域的基板支撑等离子体蚀刻系统被配置为控制预定位置的蚀刻温度，从而可以补偿临界器件参数的预蚀刻和/或蚀刻后不均匀性。

3. 发明授权

US08525139B2 Method and apparatus of halogen removal 有权
标题翻译：卤素除去的方法和装置
公开(公告)号：US08525139B2
公开(公告)日：2013-09-03
申请号：US12908258
申请日：2010-10-20
申请人： Harmeet Singh , Sanket Sant , Shang-I Chou , Vahid Vahedi , Raphael Casaes , Seetharaman Ramachandran
发明人： Harmeet Singh , Sanket Sant , Shang-I Chou , Vahid Vahedi , Raphael Casaes , Seetharaman Ramachandran
IPC分类号： A61N5/06 , C23F1/00 , H01L21/3065 , H01L21/26
CPC分类号： H01L21/02057 , H01L21/67017 , H01L21/67115 , H01L21/6719 , H01L21/67201 , H01L21/67207
摘要： A wafer is provided into an entrance load lock chamber. A vacuum is created in the entrance load lock chamber. The wafer is transported to a processing tool. The wafer is processed in a process chamber to provide a processed wafer, wherein the processing forms halogen residue. A degas step is provided in the process chamber after processing the wafer. The processed wafer is transferred into a degas chamber. The processed wafer is treated in the degas chamber with UV light and a flow of gas comprising at least one of ozone, oxygen, or H2O. The flow of gas is stopped. The UV light is stopped. The processed wafer is removed from the degas chamber.
摘要翻译：将晶片设置在入口加载锁定室中。在入口装载锁定室中产生真空。晶片被输送到处理工具。在处理室中处理晶片以提供经处理的晶片，其中处理形成卤素残基。在处理晶片之后，在处理室中提供脱气步骤。将经处理的晶片转移到脱气室中。处理的晶片在脱气室中用UV光和包含臭氧，氧气或H 2 O中的至少一种的气体流进行处理。停止气体流动。 UV灯停止。将经处理的晶片从脱气室中取出。

4. 发明授权

US07578945B2 Method and apparatus for tuning a set of plasma processing steps 有权
标题翻译：用于调整一组等离子体处理步骤的方法和装置
公开(公告)号：US07578945B2
公开(公告)日：2009-08-25
申请号：US11582730
申请日：2006-10-17
申请人： Vahid Vahedi , John Daugherty , Harmeet Singh , Anthony Chen
发明人： Vahid Vahedi , John Daugherty , Harmeet Singh , Anthony Chen
IPC分类号： B44C1/22 , H01L21/00
CPC分类号： H01L21/32136 , C03C15/00 , C03C23/006 , H01J37/32623 , H01J37/32642
摘要： In a plasma processing system, a method of tuning of a set of plasma processing steps is disclosed. The method includes striking a first plasma comprising neutrals and ions in a plasma reactor of the plasma processing system. The method also includes etching in a first etching step a set of layers on a substrate; positioning a movable uniformity ring around the substrate, wherein a bottom surface of the uniformity ring is about the same height as a top surface of the substrate; and striking a second plasma consisting essentially of neutrals in the plasma reactor of the plasma processing system. The method further includes etching in a second etching step the set of layers on the substrate; and wherein the etching in the first step and the etching in the second step are substantially uniform.
摘要翻译：在等离子体处理系统中，公开了一组等离子体处理步骤的调谐方法。该方法包括在等离子体处理系统的等离子体反应器中击打包含中性粒子和离子的第一等离子体。该方法还包括在第一蚀刻步骤中蚀刻在衬底上的一组层; 将可移动均匀环定位在基底周围，其中均匀环的底表面与基底的顶表面大致相同的高度; 并且在等离子体处理系统的等离子体反应器中击打基本上由中性体组成的第二等离子体。该方法还包括在第二蚀刻步骤中蚀刻在衬底上的一组层; 并且其中第一步骤中的蚀刻和第二步骤中的蚀刻基本上是均匀的。

5. 发明申请

US20100108261A1 LOWER ELECTRODE ASSEMBLY OF PLASMA PROCESSING CHAMBER 有权
标题翻译：等离子体处理室的下电极组件
公开(公告)号：US20100108261A1
公开(公告)日：2010-05-06
申请号：US12609377
申请日：2009-10-30
申请人： Jason Augustino , Quan Chau , Keith William Gaff , Hanh Tuong Ha , Brett C. Richardson , Harmeet Singh
发明人： Jason Augustino , Quan Chau , Keith William Gaff , Hanh Tuong Ha , Brett C. Richardson , Harmeet Singh
IPC分类号： C23F1/08 , H01L21/306
CPC分类号： H01J37/20 , H01J37/32091 , H01J37/32541 , H01J37/3255 , H01J37/32642 , H01J37/32715
摘要： A lower electrode assembly for use in a plasma processing chamber comprises a metal base and upper and lower edge rings. The metal base comprises metal plates brazed together and forming a brazed line on a lower side surface of the base, an edge ring support surface extending horizontally inwardly from the lower side surface and an upper side surface above the edge ring support surface. The upper edge ring comprises a lower surface mounted on the edge ring support surface and the lower edge ring surrounds the lower side surface of the base with a gap between opposed surfaces of the upper and lower edge rings and between the lower edge ring and the outer periphery of the base. The gap has an aspect ratio of total gap length to average gap width sufficient to impede arcing at the location of the braze line.
摘要翻译：用于等离子体处理室的下部电极组件包括金属基座和上部和下部边缘环。金属基底包括钎焊在一起的金属板，在基座的下侧表面上形成钎焊线，从下侧表面向水平方向延伸的边缘环支撑表面和在边缘环支撑表面上方的上侧表面。上边缘环包括安装在边缘环支撑表面上的下表面，并且下边缘环围绕基底的下侧表面，在上边缘环和下边缘环的相对表面之间以及下边缘环和外侧边缘环的相对表面之间具有间隙基地周边。间隙具有总间隙长度与平均间隙宽度的宽高比，足以阻止钎焊线位置处的电弧。

6. 发明申请

US20070293043A1 Edge gas injection for critical dimension uniformity improvement 有权
标题翻译：边缘气体注入用于临界尺寸均匀性改进
公开(公告)号：US20070293043A1
公开(公告)日：2007-12-20
申请号：US11455671
申请日：2006-06-20
申请人： Harmeet Singh , David Cooperberg , Vahid Vahedi
发明人： Harmeet Singh , David Cooperberg , Vahid Vahedi
IPC分类号： C23F1/00 , B44C1/22 , H01L21/302
CPC分类号： H01L21/6708 , H01J37/321 , H01J37/3244 , H01J2237/334 , H01L21/3065 , H01L21/32137
摘要： A method of etching a semiconductor substrate with improved critical dimension uniformity comprises supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber; supplying a first etch gas to a central region over the semiconductor substrate; supplying a second gas comprising at least one silicon containing gas to a peripheral region over the semiconductor substrate surrounding the central region, wherein a concentration of silicon in the second gas is greater than a concentration of silicon in the first etch gas; generating plasma from the first etch gas and second gas; and plasma etching an exposed surface of the semiconductor substrate.
摘要翻译：蚀刻具有改善的临界尺寸均匀性的半导体衬底的方法包括在电感耦合等离子体蚀刻室中的衬底支撑件上支撑半导体衬底; 向所述半导体衬底上的中心区域提供第一蚀刻气体; 将包含至少一种含硅气体的第二气体供应到围绕所述中心区域的所述半导体衬底上的周边区域，其中所述第二气体中的硅浓度大于所述第一蚀刻气体中的硅浓度; 从第一蚀刻气体和第二气体产生等离子体; 并且等离子体蚀刻半导体衬底的暴露表面。

7. 发明授权

US07186661B2 Method to improve profile control and N/P loading in dual doped gate applications 失效
标题翻译：在双掺杂栅极应用中改进轮廓控制和N / P加载的方法
公开(公告)号：US07186661B2
公开(公告)日：2007-03-06
申请号：US10607612
申请日：2003-06-27
申请人： Helene Del Puppo , Frank Lin , Chris Lee , Vahid Vahedi , Thomas A. Kamp , Alan J. Miller , Saurabh Ullal , Harmeet Singh
发明人： Helene Del Puppo , Frank Lin , Chris Lee , Vahid Vahedi , Thomas A. Kamp , Alan J. Miller , Saurabh Ullal , Harmeet Singh
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01L21/28035 , H01L21/28044 , H01L21/32137 , H01L21/823842 , H01L29/7833
摘要： A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.
摘要翻译：提供了一种在等离子体蚀刻室中蚀刻多晶硅栅极结构的方法。该方法开始于限定保护待蚀刻的多晶硅膜的图案。然后，产生等离子体。接下来，蚀刻大部分未被保护的多晶硅膜。然后，引入含硅气体，并且在引入含硅气体的同时蚀刻剩余的多晶硅膜。还提供了一种被配置为在蚀刻工艺期间引入含硅气体的蚀刻室。

8. 发明授权

US07682980B2 Method to improve profile control and N/P loading in dual doped gate applications 有权
标题翻译：在双掺杂栅极应用中改进轮廓控制和N / P加载的方法
公开(公告)号：US07682980B2
公开(公告)日：2010-03-23
申请号：US11627016
申请日：2007-01-25
申请人： Helene Del Puppo , Frank Lin , Chris Lee , Vahid Vahedi , Thomas A. Kamp , Alan J. Miller , Saurabh Ullal , Harmeet Singh
发明人： Helene Del Puppo , Frank Lin , Chris Lee , Vahid Vahedi , Thomas A. Kamp , Alan J. Miller , Saurabh Ullal , Harmeet Singh
IPC分类号： H01L21/302
CPC分类号： H01L21/32137
摘要： A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.
摘要翻译：提供了一种在等离子体蚀刻室中蚀刻多晶硅栅极结构的方法。该方法开始于限定保护待蚀刻的多晶硅膜的图案。然后，产生等离子体。接下来，蚀刻大部分未被保护的多晶硅膜。然后，引入含硅气体，并且在引入含硅气体的同时蚀刻剩余的多晶硅膜。还提供了一种被配置为在蚀刻工艺期间引入含硅气体的蚀刻室。

9. 发明申请

US20070119545A1 METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS 审中-公开
标题翻译：改进双层门控应用中的配置文件控制和N / P加载的方法
公开(公告)号：US20070119545A1
公开(公告)日：2007-05-31
申请号：US11627025
申请日：2007-01-25
申请人： Helene Del Puppo , Frank Lin , Chris Lee , Vahid Vahedi , Thomas Kamp , Alan Miller , Saurabh Ullal , Harmeet Singh
发明人： Helene Del Puppo , Frank Lin , Chris Lee , Vahid Vahedi , Thomas Kamp , Alan Miller , Saurabh Ullal , Harmeet Singh
IPC分类号： H01L21/306
CPC分类号： H01L21/32137
摘要： A semiconductor processing system is provided. The semiconductor processing system includes a chamber. The chamber includes a gas inlet, a top electrode configured to strike a plasma inside the chamber, and a support for holding a substrate. A controller configured to detect a passivation starved condition during an etching operation is provided. The controller is further configured to introduce a passivation enhancing gas through the gas inlet during the etching operation in response to detecting the passivation starved condition.
摘要翻译：提供半导体处理系统。半导体处理系统包括腔室。腔室包括气体入口，构造成撞击室内的等离子体的顶部电极和用于保持衬底的支撑件。提供了一种被配置为在蚀刻操作期间检测钝化不足状态的控制器。控制器还被配置为响应于检测到钝化不足状况而在蚀刻操作期间通过气体入口引入钝化增强气体。

10. 发明授权

US06994769B2 In-situ cleaning of a polymer coated plasma processing chamber 有权
标题翻译：聚合物涂层等离子体处理室的原位清洗
公开(公告)号：US06994769B2
公开(公告)日：2006-02-07
申请号：US10881112
申请日：2004-06-29
申请人： Harmeet Singh , John E. Daugherty , Vahid Vahedi , Saurabh J. Ullal
发明人： Harmeet Singh , John E. Daugherty , Vahid Vahedi , Saurabh J. Ullal
IPC分类号： C23F1/00
CPC分类号： H01J37/32862 , C23C16/4404 , C23C16/4405 , H01J37/321 , Y10S134/902 , Y10S438/905
摘要： An apparatus configured to remove chamber deposits between process operations is provided. The processing chamber includes a top electrode in communication with a power supply. A processing chamber defined within a base, a sidewall extending from the base, and a top disposed on the sidewall is provided. The processing chamber has an outlet enabling removal of fluids within the processing chamber. The processing chamber includes a substrate support and an inner surface of the processing chamber defined by the base, the sidewall and the top. The inner surface is coated with a fluorine containing polymer coating. The fluorine containing polymer coating is configured to release fluorine upon creation of an oxygen plasma in the processing chamber to remove a residue deposited on the fluorine containing polymer coating. The residue was deposited on the polymer coating from a processing operation performed in the processing chamber.
摘要翻译：提供一种被配置为在处理操作之间去除室沉积物的装置。处理室包括与电源连通的顶部电极。设置在基座内的处理室，从基座延伸的侧壁和设置在侧壁上的顶部。处理室具有能够去除处理室内的流体的出口。处理室包括基板支撑件和由基座，侧壁和顶部限定的处理室的内表面。内表面涂有含氟聚合物涂层。含氟聚合物涂层被配置为在处理室中产生氧等离子体时释放氟以除去沉积在含氟聚合物涂层上的残余物。残留物从处理室中进行的处理操作沉积在聚合物涂层上。

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