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1. 发明授权

US5287019A ECL to CMOS level conversion circuit 失效
标题翻译： ECL到CMOS电平转换电路
公开(公告)号：US5287019A
公开(公告)日：1994-02-15
申请号：US788369
申请日：1991-11-06
申请人： Kazuyuki Nonaka , Shinji Saito , Tetsuya Aisaka , Takehiro Akiyama , Kouzi Takekawa
发明人： Kazuyuki Nonaka , Shinji Saito , Tetsuya Aisaka , Takehiro Akiyama , Kouzi Takekawa
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/092 , H03K3/01
CPC分类号： H03K19/0016 , H03K19/017527 , H03K19/01812
摘要： A level conversion circuit includes an ECL logic circuit including a current switch circuit having first and second transistors, each of the transistors having an emitter coupled to each other and at least one thereof receiving an input signal of ECL logic level, and an output transistor coupled to a collector of at least one of the first and second transistors; a current control circuit including a current mirror circuit having third and fourth transistors, at least one of the transistors being coupled to an output end of the output transistor, and controlling a current flowing through the output to thereby carry out a level conversion of a signal at the output end; and a switch circuit operative coupled to the current control circuit. The switch circuit responds to a control signal and thus controls a supply of a current or a break thereof from the output transistor to the current control circuit. As a result, it is possible to decrease power dissipation in the present level conversion circuit without spoiling high speed operation thereof in a stand-by state of an apparatus or system to which it is applied.
摘要翻译：电平转换电路包括ECL逻辑电路，其包括具有第一和第二晶体管的电流开关电路，每个晶体管具有彼此耦合的发射极，并且其至少一个接收ECL逻辑电平的输入信号，以及耦合的输出晶体管耦合到所述第一和第二晶体管中的至少一个晶体管的集电极; 电流控制电路，包括具有第三和第四晶体管的电流镜电路，至少一个晶体管耦合到输出晶体管的输出端，并且控制流过输出的电流，从而执行信号的电平转换在输出端; 以及可操作地耦合到电流控制电路的开关电路。开关电路响应于控制信号，从而控制从输出晶体管到电流控制电路的电流或断路的供应。结果，可以在其应用的装置或系统的待机状态下降低当前电平转换电路中的功率消耗而不破坏其高速操作。

2. 发明授权

US5047733A PLL synthesizer providing rapid frequency changeover 失效
标题翻译： PLL合成器提供快速频率切换
公开(公告)号：US5047733A
公开(公告)日：1991-09-10
申请号：US454589
申请日：1989-12-21
申请人： Kazuyuki Nonaka , Takehiro Akiyama , Kouzi Takekawa
发明人： Kazuyuki Nonaka , Takehiro Akiyama , Kouzi Takekawa
IPC分类号： H03L7/187 , H03L7/089 , H03L7/107 , H03L7/183
CPC分类号： H03L7/107 , H03L7/183 , H03L7/0891
摘要： A PLL synthesizer includes a voltage-controlled oscillator generating an output signal having a frequency based on a first signal supplied thereto, a PLL control circuit which generates a second signal based on the output signal and a set frequency, a lowpass filter having an input terminal and an output terminal, for filtering the second signal supplied through the input terminal to thereby generate the first signal supplied to the voltage-controlled oscillator through the output terminal, and a switch circuit which is coupled between the input and output terminals of the lowpass filter and which supplies the second signal directly to the voltage-controlled oscillator during a predetermined time when the set frequency is changed.

3. 发明授权

US5534821A Charge pump circuits for PLL frequency synthesizer 失效
标题翻译： PLL频率合成器的电荷泵电路
公开(公告)号：US5534821A
公开(公告)日：1996-07-09
申请号：US288924
申请日：1994-08-11
申请人： Takehiro Akiyama , Katsuya Shimomura , Kouzi Takekawa , Takehito Doi
发明人： Takehiro Akiyama , Katsuya Shimomura , Kouzi Takekawa , Takehito Doi
IPC分类号： H03L7/18 , H03K17/66 , H03K17/687 , H03L7/089 , H03L7/093 , H03L7/10
CPC分类号： H03K17/666 , H03K17/667 , H03K17/6872 , H03L7/0895 , H03L7/0896
摘要： A PLL frequency synthesizer, which comprises a voltage controlled oscillator, and a comparison frequency divider for dividing a frequency of the output signal from the voltage controlled oscillator to output a comparison signal. A phase comparator in the synthesizer compares a phase of a reference signal to be fed thereto with a phase of the comparison signal, and generates first and second phase difference signals, based on the compared result. The synthesizer further includes a charge-pump circuit operated based on the first and second phase difference signals, and having an output terminal connected to the voltage controlled oscillator. The charge-pump circuit includes a first bipolar transistor connected between a high-potential power supply and the output terminal, and a second bipolar transistor connected between a low-potential power supply and the output terminal. The first and second bipolar transistors are controlled based on the first and second phase difference signals, respectively. At least one of the first and second bipolar transistors is an emitter-follower type. In another embodiment, a node is provided between two switches formed by CMOS transistors, to serve as an output terminal of the charge-pump circuit. In a further embodiment, two PMOS transistors are provided as switches, and a node is provided therebetween to serve as an output terminal of the charge-pump circuit.
摘要翻译：包括压控振荡器的PLL频率合成器和用于对来自压控振荡器的输出信号的频率进行分频以输出比较信号的比较分频器。合成器中的相位比较器将要馈送的参考信号的相位与比较信号的相位进行比较，并且基于比较结果产生第一和第二相位差信号。合成器还包括基于第一和第二相位差信号操作并具有连接到压控振荡器的输出端的电荷泵电路。电荷泵电路包括连接在高电位电源和输出端之间的第一双极晶体管和连接在低电位电源与输出端之间的第二双极晶体管。第一和第二双极晶体管分别基于第一和第二相位差信号来控制。第一和第二双极晶体管中的至少一个是发射极跟随器。在另一个实施例中，在由CMOS晶体管形成的两个开关之间提供节点，以用作电荷泵电路的输出端。在另一实施例中，提供两个PMOS晶体管作为开关，并且在其间提供节点以用作电荷泵电路的输出端子。

4. 发明授权

US4897560A Semiconductor integrated circuit with reduced power consumption 失效
标题翻译：半导体集成电路降低功耗
公开(公告)号：US4897560A
公开(公告)日：1990-01-30
申请号：US190745
申请日：1988-05-05
申请人： Shinji Saito , Kazuyuki Nonaka , Hideji Sumi , Takehiro Akiyama
发明人： Shinji Saito , Kazuyuki Nonaka , Hideji Sumi , Takehiro Akiyama
IPC分类号： H03L7/18 , H03J5/02 , H03K3/2885 , H03K17/00 , H03K17/60 , H03K19/00 , H03K19/086
CPC分类号： H03J5/0272 , H03K17/603 , H03K3/2885 , H03K2217/0036
摘要： A semiconductor integrated circuit includes a logic circuit which has first and second transistors constituting an emitter coupled transistor pair and a third transistor which is used as a constant current source, a bias circuit which includes a fourth transistor having an emitter from which a first predetermined voltage is supplied to a base of the third transistor and an impedance having one end coupled to a first power source and another end coupled to a base of the fourth transistor to supply a second predetermined voltage thereto, and a clamping circuit. The clamping circuit is OFF and does not perform a clamping operation with respect to the base of the fourth transistor when the entire semiconductor integrated circuit needs to operate. When the entire semiconductor integrated circuit does not need to operate, the clamping circuit is ON to clamp the base potential of the fourth transistor so as to reduce the power consumption of the semiconductor integrate circuit.

5. 发明授权

US4755693A ECL latch circuit insensitive to alpha ray disturbances 失效
标题翻译： ECL锁存电路对α射线干扰不敏感
公开(公告)号：US4755693A
公开(公告)日：1988-07-05
申请号：US700893
申请日：1985-02-07
申请人： Hirokazu Suzuki , Takehiro Akiyama , Teruo Morita
发明人： Hirokazu Suzuki , Takehiro Akiyama , Teruo Morita
IPC分类号： H03K3/286 , H03K3/013 , H03K3/0233 , H03K3/2885 , H03K3/01 , H03K19/086
CPC分类号： H03K3/013 , H03K3/2885
摘要： A latch circuit inputting and holding a write data including a data input terminal for receiving a write data signal and a feedback input terminal for receiving a feedback signal from an output terminal, the latch circuit through a feedback loop, wherein the output terminal of the latch circuit outputs the write data signal at a suitable timing. The latch circuit is operated such that a potential difference between a peak voltage of a logic amplitude and a reference voltage at the side at which the feedback signal is applied is set larger than a potential difference between the peak voltage of the logic amplitude and the reference voltage at the side at which the write data signal is applied.
摘要翻译：一种锁存电路，其输入并保持包括用于接收写入数据信号的数据输入端子和用于从输出端子接收反馈信号的反馈信号的写入数据，所述锁存电路通过反馈环路，其中所述锁存器的输出端子电路在适当的定时输出写数据信号。操作闩锁电路，使得逻辑振幅的峰值电压与施加反馈信号的一侧的基准电压之间的电位差设定为大于逻辑幅度的峰值电压与参考电压之间的电位差施加写入数据信号的一侧的电压。

6. 发明授权

US4748488A Master-slice-type semiconductor integrated circuit device 失效
标题翻译：主分片式半导体集成电路器件
公开(公告)号：US4748488A
公开(公告)日：1988-05-31
申请号：US653523
申请日：1984-09-24
申请人： Hirokazu Suzuki , Takehiro Akiyama , Teruo Morita
发明人： Hirokazu Suzuki , Takehiro Akiyama , Teruo Morita
IPC分类号： H01L21/822 , G11C11/401 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/118
CPC分类号： H01L21/82 , H01L23/528 , H01L27/11801 , H01L2924/0002
摘要： A master-slice-type semiconductor integrated circuit device including basic cells, each having at least one logical circuit element, and current source cells for supplying current to the basic cells, each having at least one current source element and separated from the basic cells. A logic circuit operatively connects at least one logical circuit element in one of the basic cells and at least one current source element in one of the current source cells. The basic cells are arranged in groups extending in a lateral direction of the device and form cell rows in the lateral direction with groups of current source cells periodically formed in each cell row. The groups of current source cells in different cells rows are aligned in a longitudinal direction perpendicular to the lateral direction. The logic circuit is connected by conductive strips formed in wiring channels, each wiring channel being formed parallel and adjacent to at least one cell row.
摘要翻译：包括具有至少一个逻辑电路元件的基本单元和用于向基本单元提供电流的电流源单元的主分片型半导体集成电路器件，每个基本单元具有至少一个电流源元件并与基本单元分离。逻辑电路可操作地将一个基本单元中的至少一个逻辑电路元件和当前源单元之一中的至少一个电流源元件连接起来。基本单元被布置成沿设备的横向延伸的组，并且在横向方向上形成单元行，并且每个单元行中周期性地形成有电流源单元的组。不同单元行中的电流源单元组在垂直于横向方向的纵向上对齐。逻辑电路由形成在布线通道中的导电条连接，每个布线通道平行并邻近至少一个单元行。

7. 发明授权

US4481427A TTL Circuit having delay means for delaying the operation until the supply voltage reaches a certain threshold 失效
标题翻译： TTL电路具有用于延迟操作直到电源电压达到一定阈值的延迟装置
公开(公告)号：US4481427A
公开(公告)日：1984-11-06
申请号：US445039
申请日：1982-11-29
申请人： Hirokazu Suzuki , Takehiro Akiyama
发明人： Hirokazu Suzuki , Takehiro Akiyama
IPC分类号： H03K19/003 , H03K17/22 , H03K19/088
CPC分类号： H03K17/22 , H03K2017/226
摘要： A TTL circuit including an input circuit, an output circuit, elements for controlling the output circuit, and elements for delaying the operation of the controlling elements immediately after the voltage supply is turned on. The output of the TTL circuit is maintained at on "H" level until the voltage supply rises up to a predetermined level.
摘要翻译： TTL电路包括输入电路，输出电路，用于控制输出电路的元件，以及用于在电源接通之后立即延迟控制元件的操作的元件。 TTL电路的输出保持在“H”电平，直到电压上升到预定电平。

8. 发明授权

US4645958A Variable delay gate circuit 失效
标题翻译：可变延迟门电路
公开(公告)号：US4645958A
公开(公告)日：1987-02-24
申请号：US679998
申请日：1984-12-10
申请人： Hirokazu Suzuki , Takehiro Akiyama , Teruo Morita , Hirofumi Takeda , Hikotaro Masunaga
发明人： Hirokazu Suzuki , Takehiro Akiyama , Teruo Morita , Hirofumi Takeda , Hikotaro Masunaga
IPC分类号： H03K17/296 , G01R31/319 , H03K5/13 , H03K19/086 , H03K5/159
CPC分类号： H03K5/13 , H03K19/086 , G01R31/3191
摘要： A gate circuit device of an integrated circuit tester, for variably setting the signal propagation delay time of various integrated circuits to be tested at a predetermined value, includes a gate circuit having a pair of emitter coupled transistors and a constant current source transistor connected to the emitter side of the pair of transistors, and a terminal to apply a predetermined level of voltage to the base of the constant current source transistor to control the constant current. In addition to this manner of the voltage control of signal propagation delay time, a current adjustment circuit is utilized to generate current in a constant current source transistor in response to the control current. Thus, the gate circuit device controls the signal propagation delay time by regulating either voltage or current in response to the control current.
摘要翻译：集成电路测试器的门电路装置，用于以预定值可变地设置要测试的各种集成电路的信号传播延迟时间，包括具有一对发射极耦合晶体管的栅极电路和连接到一对晶体管的发射极侧，以及向恒流源晶体管的基极施加预定电平的端子以控制恒定电流的端子。除了信号传播延迟时间的电压控制的这种方式之外，还利用电流调节电路来响应控制电流在恒流源晶体管中产生电流。因此，门电路装置通过响应于控制电流调节电压或电流来控制信号传播延迟时间。

9. 发明授权

US5410571A PLL frequency synthesizer circuit 失效
标题翻译： PLL频率合成器电路
公开(公告)号：US5410571A
公开(公告)日：1995-04-25
申请号：US121546
申请日：1993-09-16
申请人： Masayuki Yonekawa , Takehiro Akiyama , Shinji Saito , Tetsuya Aisaka , Minoru Takagi
发明人： Masayuki Yonekawa , Takehiro Akiyama , Shinji Saito , Tetsuya Aisaka , Minoru Takagi
IPC分类号： H03L7/089 , H03L7/095 , H03L7/107 , H03L7/183 , H03D3/24
CPC分类号： H03L7/107 , H03L7/0891 , H03L7/0898 , H03L7/095 , H03L7/183 , Y10S331/02
摘要： A reference frequency divider divides a clock signal into a reference frequency signal, and outputs it. A comparison frequency divider circuit divides an output signal from a voltage controlled oscillator, and outputs it as a comparison signal. The reference signal and comparison signal are coupled to a phase comparator. The phase comparator detects the phase difference between the reference signal and comparison signal, and outputs a phase difference signal. A charge pump outputs a voltage signal in response to the phase difference signal from the phase comparator. A low pass filter smooths out the voltage signal from the charge pump to remove the high frequency components, and outputs a controlled voltage signal. A voltage controlled oscillator outputs an output signal with the frequency relating to the voltage value of the controlled voltage signal from the low pass filter. A frequency difference determining circuit compares the reference signal with the comparison signal. The circuit outputs a signal indicative of the frequency locked when the frequency difference is within the preset range, and outputs a signal indicative of the frequency unlocked when the difference of the frequency exceeds the preset range.
摘要翻译：参考分频器将时钟信号分频为参考频率信号，并将其输出。比较分频器电路分压来自压控振荡器的输出信号，并将其作为比较信号输出。参考信号和比较信号耦合到相位比较器。相位比较器检测参考信号和比较信号之间的相位差，并输出相位差信号。电荷泵响应于来自相位比较器的相位差信号输出电压信号。低通滤波器平滑电荷泵的电压信号，去除高频分量，并输出受控电压信号。压控振荡器以与低通滤波器的受控电压信号的电压值相关的频率输出输出信号。频率差确定电路将参考信号与比较信号进行比较。当频率差在预设范围内时，电路输出指示频率被锁定的信号，并且当频率差超过预设范围时输出表示频率被解锁的信号。

10. 发明授权

US5180992A PLL frequency synthesizer having a power saving circuit 失效
标题翻译：具有节电电路的PLL频率合成器
公开(公告)号：US5180992A
公开(公告)日：1993-01-19
申请号：US777927
申请日：1991-10-17
申请人： Takehiro Akiyama , Kazumi Ogawa
发明人： Takehiro Akiyama , Kazumi Ogawa
IPC分类号： H03L7/18 , H03L7/08 , H03L7/087 , H03L7/199
CPC分类号： H03L7/199 , H03L7/0802 , H03L7/087 , H03L2207/18
摘要： A PLL frequency synthesizer includes a reset circuit which determines whether or not an oscillator starts to normally generate an oscillation signal in response to a power save signal which intermittently operates the oscillator in a standby mode and which outputs a reset signal to a prescaler when it is determined that the oscillator normally generates the oscillation signal. A hold circuit prevents a frequency-divided signal being output from the prescaler to a programmable counter and an initial phase detection circuit until the prescaler is reset to an initial state in response to the reset signal and starts to normally generate the frequency-divided signal.

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