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1. 发明申请

US20190221245A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER 审中-公开
公开(公告)号：US20190221245A1
公开(公告)日：2019-07-18
申请号：US16363961
申请日：2019-03-25
申请人： Micron Technology, Inc.
发明人： Tetsuya Arai , Junki Taniguchi
IPC分类号： G11C7/10 , G01R31/319 , G06F1/26
CPC分类号： G11C7/1057 , G01R31/3191 , G06F1/266 , G11C2207/2254
摘要： An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

2. 发明授权

US09851402B2 Systems and methods mitigating temperature dependence of circuitry in electronic devices 有权
公开(公告)号：US09851402B2
公开(公告)日：2017-12-26
申请号：US13960662
申请日：2013-08-06
申请人： Jeffrey Allen King
发明人： Jeffrey Allen King
IPC分类号： G01R31/00 , G01R31/319 , G01R31/28 , G01R35/00
CPC分类号： G01R31/3191 , G01R31/2879 , G01R35/005
摘要： Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

3. 发明授权

US09746520B2 Systems and methods mitigating temperature dependence of circuitry in electronic devices 有权
公开(公告)号：US09746520B2
公开(公告)日：2017-08-29
申请号：US13960566
申请日：2013-08-06
申请人： Jeffrey Allen King
发明人： Jeffrey Allen King
IPC分类号： G01R33/02 , G01R31/319 , G01R31/28 , G01R35/00
CPC分类号： G01R31/3191 , G01R31/2879 , G01R35/005
摘要： Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

4. 发明申请

US20170168100A1 PULSE GENERATING APPARATUS AND CALIBRATING METHOD THEREOF 审中-公开
公开(公告)号：US20170168100A1
公开(公告)日：2017-06-15
申请号：US15373311
申请日：2016-12-08
申请人： CHROMA ATE INC.
发明人： Cheng-Hsien CHANG , Ching-Hua CHU
IPC分类号： G01R29/02
CPC分类号： G01R29/02 , G01R31/3191 , G01R31/31922 , H03K3/011
摘要： A pulse generating apparatus capable of calibration and calibrating method are disclosed. The pulse generating apparatus includes a pulse generator and a delay detector. The pulse generator is configured to repeatedly generate a testing pulse. The delay detector is electrically connected with the pulse generator. When the pulse generator generates the testing pulse, the delay detector detects a feature value of the testing pulse at a plurality detecting time points, and calculates a calibration value according to the detected feature values. The delay detector outputs the calibration value to the pulse generator and the pulse generator adjusts the testing pulse according to the calibration value.

5. 发明授权

US09429624B2 Synchronous sampling of internal state for investigation of digital systems 有权
标题翻译：用于数字系统调查的内部状态的同步采样
公开(公告)号：US09429624B2
公开(公告)日：2016-08-30
申请号：US14255924
申请日：2014-04-17
申请人： Colin Patrick O'Flynn
发明人： Colin Patrick O'Flynn
IPC分类号： G06F7/02 , H04M13/00 , G01R31/319 , G01R31/28 , G01R31/317 , H03M1/08
CPC分类号： G01R31/3191 , G01R31/2851 , G01R31/31707 , G01R31/31726 , H03M1/08
摘要： Methods and apparatus are provided for sampling an indicator of the internal state of an embedded system or integrated circuit, where the indicator is sampled in a manner synchronous to the internal clock of the embedded system or integrated circuit. The resulting samples can be used for determining secret data within the embedded system or integrated circuit, detecting failures, or detecting counterfeit devices.
摘要翻译：提供了用于对嵌入式系统或集成电路的内部状态的指示符进行采样的方法和装置，其中以与嵌入式系统或集成电路的内部时钟同步的方式对指示符进行采样。所得到的样本可用于确定嵌入式系统或集成电路中的秘密数据，检测故障或检测假冒设备。

6. 发明授权

US09423460B2 Systems and methods mitigating temperature dependence of circuitry in electronic devices 有权
公开(公告)号：US09423460B2
公开(公告)日：2016-08-23
申请号：US13960581
申请日：2013-08-06
申请人： Analog Test Engines, Inc.
发明人： Jeffrey Allen King
IPC分类号： G01R31/319 , G01R31/28 , G01R35/00
CPC分类号： G01R31/3191 , G01R31/2879 , G01R35/005
摘要： Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

7. 发明申请

US20150323971A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER 审中-公开
标题翻译：半导体存储器件，包括输出缓冲器
公开(公告)号：US20150323971A1
公开(公告)日：2015-11-12
申请号：US14705762
申请日：2015-05-06
申请人： Micron Technology, Inc.
发明人： TETSUYA ARAI , Junki Taniguchi
IPC分类号： G06F1/26
CPC分类号： G11C7/1057 , G01R31/3191 , G06F1/266 , G11C2207/2254
摘要： An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.
摘要翻译：一种装置包括外部端子，具有对应于代码信号的阻抗的输出电路，以及校准电路，其被配置为响应于外部端子处的电压与参考电压的比较而产生代码信号，所述比较由在第一模式中的第一循环周期和在第二模式中比第一循环周期长的第二循环。

8. 发明授权

US09147620B2 Edge triggered calibration 有权
标题翻译：边沿触发校准
公开(公告)号：US09147620B2
公开(公告)日：2015-09-29
申请号：US13450123
申请日：2012-04-18
申请人： Jan Paul Anthonie van der Wagt , Ronald A. Sartschev , Gregory A. Kannall
发明人： Jan Paul Anthonie van der Wagt , Ronald A. Sartschev , Gregory A. Kannall
IPC分类号： G06F17/30 , H01L21/66 , G01R31/319
CPC分类号： H01L22/34 , G01R31/3191 , G01R31/31922 , H01L2924/0002 , H01L2924/00
摘要： Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one-shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system.
摘要翻译：用于测量电路路径中的传播延迟的电路。电路包括可以与电路路径连接的单触发边沿触发元件。通过电路路径传播的边沿信号触发单触发元件输出脉冲。脉冲在环路周围传播，再次触发单触发元件产生脉冲，产生重复的脉冲序列。这些脉冲之间的周期受到通过环路的边缘的传播时间的影响，使得与环路中连接并未连接的电路路径的周期的差异指示电路路径中的传播延迟。这样的电路可以被配置为独立地测量并因此校准与上升沿和下降沿相关联的传播延迟。校准以分别均衡上升沿和下降沿的传播延迟可以增加自动测试系统的定时精度。

9. 发明申请

US20150253388A1 TEST APPARATUS, TEST METHOD, CALIBRATION DEVICE, AND CALIBRATION METHOD 有权
标题翻译：测试装置，测试方法，校准装置和校准方法
公开(公告)号：US20150253388A1
公开(公告)日：2015-09-10
申请号：US14633148
申请日：2015-02-27
申请人： ADVANTEST CORPORATION
发明人： Shin MASUDA , Hideo HARA , Tsuyoshi ATAKA
IPC分类号： G01R31/319 , G01R31/3163 , G01R31/317
CPC分类号： G01R31/31917 , G01R31/3163 , G01R31/31713 , G01R31/31901 , G01R31/3191
摘要： Provided is a test apparatus including an optical test signal generating section that generates an optical test signal; an optical signal supplying section that supplies the optical test signal to a device under test that is a testing target among a plurality of the devices under test; a first optical switch section that selects, from among optical signals output by the plurality of devices under test, the optical signal output by the device under test that is the testing target; and an optical signal receiving section that receives the selected optical signal.
摘要翻译：提供了一种测试装置，其包括产生光学测试信号的光学测试信号产生部分; 光信号提供部，将光测试信号供给到被测设备，被测设备是被测设备的多个测试对象; 第一光开关部，从被测试的多个被测设备输出的光信号中，选择被作为测试目标的被测器件输出的光信号; 以及光信号接收部，其接收所选择的光信号。

10. 发明授权

US09015541B2 Device and method for performing timing analysis 有权
标题翻译：用于执行时序分析的装置和方法
公开(公告)号：US09015541B2
公开(公告)日：2015-04-21
申请号：US13798879
申请日：2013-03-13
申请人： Test Research, Inc.
发明人： Yu-Chen Shen , Yi-Hao Hsu
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/3191 , G01R31/31937
摘要： A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.
摘要翻译：提供了一种用于在可编程逻辑阵列系统中使用的时序分析的装置。该器件包括第一和第二基本I / O端子，通道多路复用器，高速I / O端子，采样模块和定时分析模块。第一个基本的I / O终端从受测单元接收未测试信号。信道多路复用器从第一基本I / O终端接收欠测信号，以选择要输出到第二基本I / O终端的至少一组未测试信号。高速I / O端子的逻辑电平分析速度高于第一和第二基本I / O端子。采样模块从高速I / O端子接收一组不足的测试信号，对未测试信号组进行采样以产生采样结果。定时分析模块根据样品结果进行定时分析和测量。

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