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1. 发明授权

US4897560A Semiconductor integrated circuit with reduced power consumption 失效
标题翻译：半导体集成电路降低功耗
公开(公告)号：US4897560A
公开(公告)日：1990-01-30
申请号：US190745
申请日：1988-05-05
申请人： Shinji Saito , Kazuyuki Nonaka , Hideji Sumi , Takehiro Akiyama
发明人： Shinji Saito , Kazuyuki Nonaka , Hideji Sumi , Takehiro Akiyama
IPC分类号： H03L7/18 , H03J5/02 , H03K3/2885 , H03K17/00 , H03K17/60 , H03K19/00 , H03K19/086
CPC分类号： H03J5/0272 , H03K17/603 , H03K3/2885 , H03K2217/0036
摘要： A semiconductor integrated circuit includes a logic circuit which has first and second transistors constituting an emitter coupled transistor pair and a third transistor which is used as a constant current source, a bias circuit which includes a fourth transistor having an emitter from which a first predetermined voltage is supplied to a base of the third transistor and an impedance having one end coupled to a first power source and another end coupled to a base of the fourth transistor to supply a second predetermined voltage thereto, and a clamping circuit. The clamping circuit is OFF and does not perform a clamping operation with respect to the base of the fourth transistor when the entire semiconductor integrated circuit needs to operate. When the entire semiconductor integrated circuit does not need to operate, the clamping circuit is ON to clamp the base potential of the fourth transistor so as to reduce the power consumption of the semiconductor integrate circuit.

2. 发明授权

US5287019A ECL to CMOS level conversion circuit 失效
标题翻译： ECL到CMOS电平转换电路
公开(公告)号：US5287019A
公开(公告)日：1994-02-15
申请号：US788369
申请日：1991-11-06
申请人： Kazuyuki Nonaka , Shinji Saito , Tetsuya Aisaka , Takehiro Akiyama , Kouzi Takekawa
发明人： Kazuyuki Nonaka , Shinji Saito , Tetsuya Aisaka , Takehiro Akiyama , Kouzi Takekawa
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/092 , H03K3/01
CPC分类号： H03K19/0016 , H03K19/017527 , H03K19/01812
摘要： A level conversion circuit includes an ECL logic circuit including a current switch circuit having first and second transistors, each of the transistors having an emitter coupled to each other and at least one thereof receiving an input signal of ECL logic level, and an output transistor coupled to a collector of at least one of the first and second transistors; a current control circuit including a current mirror circuit having third and fourth transistors, at least one of the transistors being coupled to an output end of the output transistor, and controlling a current flowing through the output to thereby carry out a level conversion of a signal at the output end; and a switch circuit operative coupled to the current control circuit. The switch circuit responds to a control signal and thus controls a supply of a current or a break thereof from the output transistor to the current control circuit. As a result, it is possible to decrease power dissipation in the present level conversion circuit without spoiling high speed operation thereof in a stand-by state of an apparatus or system to which it is applied.
摘要翻译：电平转换电路包括ECL逻辑电路，其包括具有第一和第二晶体管的电流开关电路，每个晶体管具有彼此耦合的发射极，并且其至少一个接收ECL逻辑电平的输入信号，以及耦合的输出晶体管耦合到所述第一和第二晶体管中的至少一个晶体管的集电极; 电流控制电路，包括具有第三和第四晶体管的电流镜电路，至少一个晶体管耦合到输出晶体管的输出端，并且控制流过输出的电流，从而执行信号的电平转换在输出端; 以及可操作地耦合到电流控制电路的开关电路。开关电路响应于控制信号，从而控制从输出晶体管到电流控制电路的电流或断路的供应。结果，可以在其应用的装置或系统的待机状态下降低当前电平转换电路中的功率消耗而不破坏其高速操作。

3. 发明授权

US5047733A PLL synthesizer providing rapid frequency changeover 失效
标题翻译： PLL合成器提供快速频率切换
公开(公告)号：US5047733A
公开(公告)日：1991-09-10
申请号：US454589
申请日：1989-12-21
申请人： Kazuyuki Nonaka , Takehiro Akiyama , Kouzi Takekawa
发明人： Kazuyuki Nonaka , Takehiro Akiyama , Kouzi Takekawa
IPC分类号： H03L7/187 , H03L7/089 , H03L7/107 , H03L7/183
CPC分类号： H03L7/107 , H03L7/183 , H03L7/0891
摘要： A PLL synthesizer includes a voltage-controlled oscillator generating an output signal having a frequency based on a first signal supplied thereto, a PLL control circuit which generates a second signal based on the output signal and a set frequency, a lowpass filter having an input terminal and an output terminal, for filtering the second signal supplied through the input terminal to thereby generate the first signal supplied to the voltage-controlled oscillator through the output terminal, and a switch circuit which is coupled between the input and output terminals of the lowpass filter and which supplies the second signal directly to the voltage-controlled oscillator during a predetermined time when the set frequency is changed.

4. 发明授权

US5594382A Constant voltage circuit 失效
标题翻译：恒压电路
公开(公告)号：US5594382A
公开(公告)日：1997-01-14
申请号：US407248
申请日：1995-03-20
申请人： Susumu Kato , Moriaki Mizuno , Kazumi Ogawa , Kazuyuki Nonaka
发明人： Susumu Kato , Moriaki Mizuno , Kazumi Ogawa , Kazuyuki Nonaka
IPC分类号： G05F3/30 , G05F3/26 , G05F1/10 , G05F3/02
CPC分类号： G05F3/267
摘要： A constant voltage circuit adapted for connection between high voltage power source and low voltage power source terminals respectively to output a constant voltage signal from an output terminal in response to a control signal inputted to an input terminal. The circuit has a resistor circuit including a MOS transistor for connection to the high voltage power source and activated in response to the control signal. A current mirror section is connected between the resistor circuit and the low voltage power source terminal to generate an output voltage to be outputted from the output terminal. A feedback section is connected between the resistor circuit and the low voltage power source terminal to control the current mirror section to keep the output voltage constant by detecting deviation of the output voltage.
摘要翻译：一种恒压电路，分别适于连接高电压电源和低电压电源端子，以响应输入到输入端子的控制信号从输出端输出恒定电压信号。电路具有包括用于连接到高电压电源并且响应于控制信号激活的MOS晶体管的电阻器电路。电流镜部分连接在电阻器电路和低压电源端子之间，以产生从输出端子输出的输出电压。反馈部分连接在电阻电路和低压电源端子之间，以通过检测输出电压的偏差来控制电流镜部分以保持输出电压恒定。

5. 发明授权

US5218238A Bias voltage generation circuit of ECL level for decreasing power consumption thereof 失效
标题翻译：用于降低电力消耗的电压等级电压产生电路
公开(公告)号：US5218238A
公开(公告)日：1993-06-08
申请号：US851431
申请日：1992-03-13
申请人： Kazuyuki Nonaka , Tetsuya Aisaka
发明人： Kazuyuki Nonaka , Tetsuya Aisaka
IPC分类号： G05F3/22 , G05F3/30 , H03K19/00 , H03K19/086
CPC分类号： H03K19/086 , G05F3/22 , G05F3/30 , H03K19/0016
摘要： A bias voltage generation circuit comprises a bias voltage generation portion having a bias control node, a first switching unit, and a second switching unit. The bias voltage generation portion is used to generate a bias voltage of a predetermined potential and supply the bias voltage to an ECL circuit during an operation period, and the first switching unit is used to drop the bias voltage during a standby period in response to a bias voltage control signal. The second switching unit is used to switch OFF during the standby period to cut off a current flow through the bias control node and switch ON during the operation period to supply a current through the bias control node in response to the bias voltage control signal. Consequently, a current flow during the standby period can be reduced, and power consumption of the bias voltage generation circuit during the standby period is minimal.

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