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1. 发明授权

US5410571A PLL frequency synthesizer circuit 失效
标题翻译： PLL频率合成器电路
公开(公告)号：US5410571A
公开(公告)日：1995-04-25
申请号：US121546
申请日：1993-09-16
申请人： Masayuki Yonekawa , Takehiro Akiyama , Shinji Saito , Tetsuya Aisaka , Minoru Takagi
发明人： Masayuki Yonekawa , Takehiro Akiyama , Shinji Saito , Tetsuya Aisaka , Minoru Takagi
IPC分类号： H03L7/089 , H03L7/095 , H03L7/107 , H03L7/183 , H03D3/24
CPC分类号： H03L7/107 , H03L7/0891 , H03L7/0898 , H03L7/095 , H03L7/183 , Y10S331/02
摘要： A reference frequency divider divides a clock signal into a reference frequency signal, and outputs it. A comparison frequency divider circuit divides an output signal from a voltage controlled oscillator, and outputs it as a comparison signal. The reference signal and comparison signal are coupled to a phase comparator. The phase comparator detects the phase difference between the reference signal and comparison signal, and outputs a phase difference signal. A charge pump outputs a voltage signal in response to the phase difference signal from the phase comparator. A low pass filter smooths out the voltage signal from the charge pump to remove the high frequency components, and outputs a controlled voltage signal. A voltage controlled oscillator outputs an output signal with the frequency relating to the voltage value of the controlled voltage signal from the low pass filter. A frequency difference determining circuit compares the reference signal with the comparison signal. The circuit outputs a signal indicative of the frequency locked when the frequency difference is within the preset range, and outputs a signal indicative of the frequency unlocked when the difference of the frequency exceeds the preset range.
摘要翻译：参考分频器将时钟信号分频为参考频率信号，并将其输出。比较分频器电路分压来自压控振荡器的输出信号，并将其作为比较信号输出。参考信号和比较信号耦合到相位比较器。相位比较器检测参考信号和比较信号之间的相位差，并输出相位差信号。电荷泵响应于来自相位比较器的相位差信号输出电压信号。低通滤波器平滑电荷泵的电压信号，去除高频分量，并输出受控电压信号。压控振荡器以与低通滤波器的受控电压信号的电压值相关的频率输出输出信号。频率差确定电路将参考信号与比较信号进行比较。当频率差在预设范围内时，电路输出指示频率被锁定的信号，并且当频率差超过预设范围时输出表示频率被解锁的信号。

2. 发明授权

US5287019A ECL to CMOS level conversion circuit 失效
标题翻译： ECL到CMOS电平转换电路
公开(公告)号：US5287019A
公开(公告)日：1994-02-15
申请号：US788369
申请日：1991-11-06
申请人： Kazuyuki Nonaka , Shinji Saito , Tetsuya Aisaka , Takehiro Akiyama , Kouzi Takekawa
发明人： Kazuyuki Nonaka , Shinji Saito , Tetsuya Aisaka , Takehiro Akiyama , Kouzi Takekawa
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/092 , H03K3/01
CPC分类号： H03K19/0016 , H03K19/017527 , H03K19/01812
摘要： A level conversion circuit includes an ECL logic circuit including a current switch circuit having first and second transistors, each of the transistors having an emitter coupled to each other and at least one thereof receiving an input signal of ECL logic level, and an output transistor coupled to a collector of at least one of the first and second transistors; a current control circuit including a current mirror circuit having third and fourth transistors, at least one of the transistors being coupled to an output end of the output transistor, and controlling a current flowing through the output to thereby carry out a level conversion of a signal at the output end; and a switch circuit operative coupled to the current control circuit. The switch circuit responds to a control signal and thus controls a supply of a current or a break thereof from the output transistor to the current control circuit. As a result, it is possible to decrease power dissipation in the present level conversion circuit without spoiling high speed operation thereof in a stand-by state of an apparatus or system to which it is applied.
摘要翻译：电平转换电路包括ECL逻辑电路，其包括具有第一和第二晶体管的电流开关电路，每个晶体管具有彼此耦合的发射极，并且其至少一个接收ECL逻辑电平的输入信号，以及耦合的输出晶体管耦合到所述第一和第二晶体管中的至少一个晶体管的集电极; 电流控制电路，包括具有第三和第四晶体管的电流镜电路，至少一个晶体管耦合到输出晶体管的输出端，并且控制流过输出的电流，从而执行信号的电平转换在输出端; 以及可操作地耦合到电流控制电路的开关电路。开关电路响应于控制信号，从而控制从输出晶体管到电流控制电路的电流或断路的供应。结果，可以在其应用的装置或系统的待机状态下降低当前电平转换电路中的功率消耗而不破坏其高速操作。

3. 发明授权

US5878101A Swallow counter with modulus signal output control 失效
公开(公告)号：US5878101A
公开(公告)日：1999-03-02
申请号：US763402
申请日：1996-12-11
申请人： Tetsuya Aisaka
发明人： Tetsuya Aisaka
IPC分类号： H03L7/197 , H03K21/40 , H03K23/66 , H03L7/08 , H03L7/183 , H03L7/193 , H03K21/00
CPC分类号： H03K23/665 , H03L7/193
摘要： Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio. If the set value data is data for fixing the frequency-dividing ratio, the swallow counter operates in such a manner so as to restrict supply of the modulus signal, originated from the set value data, to the prescaler. The swallow counter may be included in a comparison frequency divider for supplying a comparison signal to a phase comparator in a PLL frequency synthesizer circuit that includes a voltage controlled oscillator.

4. 发明授权

US5162676A Circuit having level converting circuit for converting logic level 失效
标题翻译：具有转换逻辑电平的电平转换电路的电路
公开(公告)号：US5162676A
公开(公告)日：1992-11-10
申请号：US669987
申请日：1991-03-15
申请人： Kouju Aoki , Hideji Sumi , Moriaki Mizuno , Tetsuya Aisaka
发明人： Kouju Aoki , Hideji Sumi , Moriaki Mizuno , Tetsuya Aisaka
IPC分类号： H03K19/018 , H03K19/086
CPC分类号： H03K19/01812 , H03K19/086
摘要： A circuit has a level converting circuit for converting a signal having level in conformance with a first logic system into a signal having a level in conformance with a second logic system. The circuit includes first, second and third voltage lines for respectively supplying first, second and third power source voltages, a level converting circuit coupled to the first and third voltage lines for converting a first signal having a level in conformance with the first logic system into a second signal having a level in conformance with the second logic system, a reference voltage generating part coupled to the first and third voltage lines for generating a reference voltage based on at least the first power source voltage, so that the reference voltage undergoes a corresponding level deviation with respect to a level deviation of the second signal caused by a level deviation in the first signal which occurs due to a level deviation in the first power source voltage, and a logic circuit which employs the second logic system and is coupled to the second and third voltage lines for receiving the second signal from the level converting circuit and for outputting an output signal using the reference voltage from the reference voltage generating part as a bias signal. The first power source voltage is a positive voltage relative to the second power source voltage and the third power source voltage is a negative voltage relative to the second power source voltage.

5. 发明授权

US5982840A Swallow counter with modulus signal output control 失效
标题翻译：燕窝计数器具有模数信号输出控制
公开(公告)号：US5982840A
公开(公告)日：1999-11-09
申请号：US196324
申请日：1998-11-19
申请人： Tetsuya Aisaka
发明人： Tetsuya Aisaka
IPC分类号： H03L7/197 , H03K21/40 , H03K23/66 , H03L7/08 , H03L7/183 , H03L7/193 , G06M3/00
CPC分类号： H03K23/665 , H03L7/193
摘要： Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio. If the set value data is data for fixing the frequency-dividing ratio, the swallow counter operates in such a manner so as to restrict supply of the modulus signal, originated from the set value data, to the prescaler. The swallow counter may be included in a comparison frequency divider for supplying a comparison signal to a phase comparator in a PLL frequency synthesizer circuit that includes a voltage controlled oscillator.
摘要翻译：改进的PLL频率合成器电路，包括一个新颖的吞咽计数器，可以高速运行，而不会遇到内部延迟或故障。燕子计数器向预分频器提供模数信号，该预分频器能够选择性地改变频率信号的分频比。吞咽计数器包括移位寄存器，计数器，计数检测器，模数信号发生器和控制电路。燕子计数器连接到预分频器和程序计数器，并且能够基于设定值数据对分频信号进行计数，并且在计数完成之后响应于负载信号产生模数信号。燕窝计数器向预分频器提供模数信号，并确定设定值数据是否准备好固定分频比的数据。如果设定值数据是用于固定分频比的数据，则吞吐计数器以这样的方式操作，以便将来自设定值数据的模数信号的供给限制到预分频器。吞咽计数器可以包括在比较分频器中，用于在包括压控振荡器的PLL频率合成器电路中向比较器提供比较信号。

6. 发明授权

US5218238A Bias voltage generation circuit of ECL level for decreasing power consumption thereof 失效
标题翻译：用于降低电力消耗的电压等级电压产生电路
公开(公告)号：US5218238A
公开(公告)日：1993-06-08
申请号：US851431
申请日：1992-03-13
申请人： Kazuyuki Nonaka , Tetsuya Aisaka
发明人： Kazuyuki Nonaka , Tetsuya Aisaka
IPC分类号： G05F3/22 , G05F3/30 , H03K19/00 , H03K19/086
CPC分类号： H03K19/086 , G05F3/22 , G05F3/30 , H03K19/0016
摘要： A bias voltage generation circuit comprises a bias voltage generation portion having a bias control node, a first switching unit, and a second switching unit. The bias voltage generation portion is used to generate a bias voltage of a predetermined potential and supply the bias voltage to an ECL circuit during an operation period, and the first switching unit is used to drop the bias voltage during a standby period in response to a bias voltage control signal. The second switching unit is used to switch OFF during the standby period to cut off a current flow through the bias control node and switch ON during the operation period to supply a current through the bias control node in response to the bias voltage control signal. Consequently, a current flow during the standby period can be reduced, and power consumption of the bias voltage generation circuit during the standby period is minimal.

7. 发明授权

US5248909A ECL-to-GaAs level converting circuit 失效
标题翻译： ECL-TO-GaAs电平转换电路
公开(公告)号：US5248909A
公开(公告)日：1993-09-28
申请号：US919371
申请日：1992-07-29
申请人： Kouju Aoki , Hideji Sumi , Moriaki Mizuno , Tetsuya Aisaka
发明人： Kouju Aoki , Hideji Sumi , Moriaki Mizuno , Tetsuya Aisaka
IPC分类号： H03K19/003 , H03K19/018
CPC分类号： H03K19/01812 , H03K19/00376
摘要： A level converting circuit converts a first signal which has an ECL level which is used in an ECL device into a second signal which has a GaAs logic level which is used in a GaAs device which is based on a GaAs substrate.
摘要翻译：电平转换电路将具有ECL装置中使用的ECL电平的第一信号转换为具有基于GaAs衬底的GaAs器件中使用的GaAs逻辑电平的第二信号。

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