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1. 发明授权

US06226079B1 Defect assessing apparatus and method, and semiconductor manufacturing method 有权
标题翻译：缺陷评估装置和方法以及半导体制造方法
公开(公告)号：US06226079B1
公开(公告)日：2001-05-01
申请号：US09161393
申请日：1998-09-29
申请人： Kazuo Takeda , Makoto Ohkura , Seiichi Isomae , Kyoko Minowa , Muneo Maeshima , Shigeru Matsui , Yasushi Matsuda , Hirofumi Shimizu
发明人： Kazuo Takeda , Makoto Ohkura , Seiichi Isomae , Kyoko Minowa , Muneo Maeshima , Shigeru Matsui , Yasushi Matsuda , Hirofumi Shimizu
IPC分类号： G01N2100
CPC分类号： G01N21/9501 , G01N21/47
摘要： A defect assessing apparatus and method and a semiconductor manufacturing method for revealing the relationship between the size and depth of defects is disclosed. A detecting optical system is provided for detecting the intensity of scattered light from a defect generated by the shorter wavelength one of the light rays of at least two different wavelengths emitted from irradiating optical systems and that of scattered light from the defect generated by the longer wavelength one of same. A calculating means is provided for determining, from the scattered light intensity derived from the shorter wavelength ray and that derived form the longer wavelength ray, both detected by the detecting optical system, a value corresponding to the defect size and another value corresponding to the defect depth. A display means is provided for displaying a distribution revealing the relationship between defect size and defect depth on the basis of the value corresponding to the defect size and the value corresponding to the defect depth, both determined by the calculating means.
摘要翻译：公开了一种用于揭示缺陷的尺寸和深度之间的关系的缺陷评估装置和方法以及半导体制造方法。提供了一种检测光学系统，用于检测由照射光学系统发射的至少两种不同波长的较短波长的一个光线产生的缺陷的散射光的强度，以及来自由较长波长产生的缺陷的散射光一个是相同的提供了一种计算装置，用于根据由检测光学系统检测的来自较短波长的衍射的散射光强度和由较长波长的光导出的值，确定对应于缺陷尺寸的值和对应于缺陷的另一个值深度。提供显示装置，用于根据由计算装置确定的缺陷尺寸和对应于缺陷深度的值，显示出显示缺陷尺寸和缺陷深度之间的关系的分布。

2. 发明授权

US06198157B1 Semiconductor device having buried boron and carbon regions 失效
标题翻译：具有埋置硼和碳区域的半导体器件
公开(公告)号：US06198157B1
公开(公告)日：2001-03-06
申请号：US09024661
申请日：1998-02-17
申请人： Hidetsugu Ishida , Seiichi Isomae
发明人： Hidetsugu Ishida , Seiichi Isomae
IPC分类号： H01L29167
CPC分类号： H01L29/167 , H01L21/26506 , H01L21/3221 , H01L29/161 , Y10S257/913 , Y10S257/914
摘要： To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.
摘要翻译：为了通过离子注入硼来提高吸杂性能，通过使用质量好的外延晶片，可以提高半导体器件的制造成本，从而抑制位错的发生。为此，形成外延层，其中形成约1μm的外延层提供注入硼离子的CZ半导体衬底，其是掺杂剂和不是掺杂剂的碳离子，并且在外延层的表面上形成晶体管。

3. 发明授权

US06635950B1 Semiconductor device having buried boron and carbon regions, and method of manufacture thereof 失效
标题翻译：具有埋藏硼和碳区域的半导体器件及其制造方法
公开(公告)号：US06635950B1
公开(公告)日：2003-10-21
申请号：US09665616
申请日：2000-09-19
申请人： Hidetsugu Ishida , Seiichi Isomae
发明人： Hidetsugu Ishida , Seiichi Isomae
IPC分类号： H01L29167
CPC分类号： H01L29/167 , H01L21/26506 , H01L21/3221 , H01L29/161 , Y10S257/913 , Y10S257/914
摘要： To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.
摘要翻译：为了通过离子注入硼来提高吸杂性能，通过使用质量好的外延晶片，可以提高半导体器件的制造成本，从而抑制位错的发生。为此，形成外延层，其中形成约1μm的外延层提供注入硼离子的CZ半导体衬底，其是掺杂剂和不是掺杂剂的碳离子，并且在外延层的表面上形成晶体管。

4. 发明授权

US07189278B2 Method and apparatus for producing semiconductor or metal particles 有权
标题翻译：用于制造半导体或金属颗粒的方法和装置
公开(公告)号：US07189278B2
公开(公告)日：2007-03-13
申请号：US10418317
申请日：2003-04-18
申请人： Kenji Kato , Yukio Yamaguchi , Seiichi Isomae , Masaki Miyazaki
发明人： Kenji Kato , Yukio Yamaguchi , Seiichi Isomae , Masaki Miyazaki
IPC分类号： B22F9/06
CPC分类号： B22F9/08 , B01J2/04 , B22F2009/0816 , B22F2009/0888 , B22F2009/0892
摘要： A method for producing semiconductor or metal particles comprises the steps of: storing a semiconductor or metal melt in a crucible having a nozzle; supplying a gas comprising at least one selected from the group consisting of He, Ne, Ar, Kr and Xe into the crucible such that the pressure of the supplied gas in a space over the melt in the crucible is higher than the pressure of a gaseous phase into which the melt is dropped; dropping the melt from the nozzle into the gaseous phase by the pressure of the gas to form liquid particles; and solidifying the liquid particles in the gaseous phase to obtain semiconductor or metal particles. The crucible comprises at least one selected from the group consisting of hexagonal BN, cubic BN, Si3N4, TiB2, ZrB2, zirconia and stabilized zirconia at least near the nozzle. Alternatively, the crucible comprises quartz glass at least near the nozzle and has a heat-resistant support member for suppressing deformation caused by a decrease in viscosity of the quartz glass at high temperatures.
摘要翻译：一种制造半导体或金属颗粒的方法包括以下步骤：将半导体或金属熔体储存在具有喷嘴的坩埚中; 将包含选自He，Ne，Ar，Kr和Xe中的至少一种的气体供应到坩埚中，使得在坩埚中的熔体上方的供应气体的压力高于气体的压力熔体滴入其中的相; 通过气体的压力将熔体从喷嘴滴入气相中以形成液体颗粒; 并使气相中的液体颗粒固化，得到半导体或金属颗粒。所述坩埚包括选自六方晶系BN，立方BN，Si 3 N 4 N，TiB 2 N，ZrB，SUB的至少一种至少在喷嘴附近，氧化锆和稳定的氧化锆。或者，坩埚包括至少在喷嘴附近的石英玻璃，并且具有用于抑制在高温下石英玻璃的粘度降低引起的变形的耐热支撑构件。

5. 发明授权

US4768076A Recrystallized CMOS with different crystal planes 失效
标题翻译：具有不同晶面的重结晶CMOS
公开(公告)号：US4768076A
公开(公告)日：1988-08-30
申请号：US774705
申请日：1985-09-11
申请人： Masaaki Aoki , Toshiaki Masuhara , Terunori Warabisako , Shoji Hanamura , Yoshio Sakai , Seiichi Isomae , Satoshi Meguro , Shuji Ikeda
发明人： Masaaki Aoki , Toshiaki Masuhara , Terunori Warabisako , Shoji Hanamura , Yoshio Sakai , Seiichi Isomae , Satoshi Meguro , Shuji Ikeda
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L29/04 , H01L27/04
CPC分类号： H01L29/045 , H01L21/8221 , H01L27/0688 , H01L27/0922
摘要： A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100.degree. K. or lower), and helps operate the device at high speeds.
摘要翻译：在具有平面方位（110）或（023）或靠近其的平面方位（与上述平面平行的方位角）的半导体晶体表面上形成CMOS IC，以便提高操作。在低温下，载流子迁移率对平面方位角的依赖性变得更显着，如图3所示。 1，并且根据平面放大移动性的差异。因此，当CMOS器件在低温（例如100°K或更低）下工作时，使用上述晶面有助于产生很大的效果，并且有助于高速操作器件。

6. 发明授权

US4126880A Germanium-containing silicon nitride film 失效
标题翻译：含锗氮化硅膜
公开(公告)号：US4126880A
公开(公告)日：1978-11-21
申请号：US756863
申请日：1977-01-04
申请人： Yoichi Tamaki , Seiichi Isomae , Masahiko Ogirima , Akira Shintani , Michiyoshi Maki
发明人： Yoichi Tamaki , Seiichi Isomae , Masahiko Ogirima , Akira Shintani , Michiyoshi Maki
IPC分类号： H01L21/318 , H01L21/32 , B05D5/12 , B32B9/04 , C04B35/16 , H01L29/14
CPC分类号： H01L21/318 , H01L21/32 , Y10T428/265
摘要： A germanium-containing silicon nitride film has a germanium content of 0.5 to 10 atomic-% that of the silicon content. Since the film has a much smaller stress than a conventional silicon nitride (Si.sub.3 N.sub.4) film, it is very suitable as a mask for fabricating a semiconductor device and an insulating or a protective film for a semiconductor device.
摘要翻译：含锗氮化硅膜的锗含量为硅含量的0.5〜10原子％。由于膜具有比常规氮化硅（Si 3 N 4）膜小得多的应力，因此非常适合用作制造半导体器件的掩模和用于半导体器件的绝缘或保护膜。

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