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1. 发明授权

US06462373B2 Nonvolatile semiconductor memory device having tapered portion on side wall of charge accumulation layer 失效
标题翻译：非易失性半导体存储器件在电荷累积层的侧壁上具有锥形部分
公开(公告)号：US06462373B2
公开(公告)日：2002-10-08
申请号：US09725564
申请日：2000-11-30
申请人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
发明人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.
摘要翻译：在非易失性半导体存储器件中，在相邻的两个器件隔离区域之间形成电荷累积层，夹在器件隔离区域的电荷累积层的至少一部分具有各自具有80度以上的锥角的侧壁使得下端的电荷累积层的宽度比上端的宽度宽，器件隔离区域的开口尺寸为0.25μm以下，存储单元的栅极长度为0.2μm以下。

2. 发明授权

US07795667B2 Semiconductor memory preventing an electric short circuit between a word line and a semiconductor substrate, and manufacturing method for the semiconductor memory 失效
标题翻译：防止字线和半导体基板之间的电短路的半导体存储器以及半导体存储器的制造方法
公开(公告)号：US07795667B2
公开(公告)日：2010-09-14
申请号：US10612033
申请日：2003-07-03
申请人： Tadashi Iguchi , Katsuhiro Ishida , Hiroaki Tsunoda , Hirohisa Iizuka , Hiroaki Hazama , Seiichi Mori
发明人： Tadashi Iguchi , Katsuhiro Ishida , Hiroaki Tsunoda , Hirohisa Iizuka , Hiroaki Hazama , Seiichi Mori
IPC分类号： H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.
摘要翻译：半导体器件包括非易失性存储器，其包括存储单元阵列，元件隔离区，第二沟槽和字线。存储单元阵列由具有浮置电极且在半导体衬底上以矩阵形状排列的存储单元构成。每个元件隔离区域具有形成在半导体衬底中的第一沟槽和沿着栅极宽度方向彼此相邻的存储单元和填充在第一沟槽中的隔离填料。第二沟槽形成在隔离填料中并且沿着栅极宽度方向彼此相邻的存储单元的浮置电极之间，并且在其底部处窄。字线连接到存储单元，埋在第二沟槽中并沿着栅极宽度方向延伸。

3. 发明授权

US06933194B2 Method of manufacturing semiconductor device using STI technique 失效
标题翻译：使用STI技术制造半导体器件的方法
公开(公告)号：US06933194B2
公开(公告)日：2005-08-23
申请号：US10670249
申请日：2003-09-26
申请人： Kazuhito Narita , Eiji Sakagami , Hiroaki Tsunoda , Masahisa Sonoda , Hideyuki Kobayashi
发明人： Kazuhito Narita , Eiji Sakagami , Hiroaki Tsunoda , Masahisa Sonoda , Hideyuki Kobayashi
IPC分类号： H01L21/28 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/76224 , H01L21/823481 , H01L27/115
摘要： A method of manufacturing a semiconductor device including forming a laminate structure which includes a gate insulation film on a semiconductor substrate and a gate electrode material film on the gate insulation film, processing the gate electrode material film to obtain a gate electrode having a reverse tapered cross section, and forming a device isolation insulation film in direct contact with a side surface of the gate electrode.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成包括栅极绝缘膜的层叠结构和栅极绝缘膜上的栅电极材料膜，处理栅电极材料膜以获得具有反向锥形交叉的栅电极并且形成与栅电极的侧表面直接接触的器件隔离绝缘膜。

4. 发明授权

US06642568B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06642568B2
公开(公告)日：2003-11-04
申请号：US09892487
申请日：2001-06-28
申请人： Kazuhito Narita , Eiji Sakagami , Hiroaki Tsunoda , Masahisa Sonoda , Hideyuki Kobayashi
发明人： Kazuhito Narita , Eiji Sakagami , Hiroaki Tsunoda , Masahisa Sonoda , Hideyuki Kobayashi
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L21/76224 , H01L21/823481 , H01L27/115
摘要： This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.

5. 发明申请

US20060018181A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20060018181A1
公开(公告)日：2006-01-26
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C8/00
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

6. 发明授权

US06984858B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06984858B2
公开(公告)日：2006-01-10
申请号：US10293254
申请日：2002-11-14
申请人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
发明人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
IPC分类号： H01L27/108
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.
摘要翻译：在包括多个元件区域的半导体器件和基于将元件区域彼此电隔离的STI（浅沟槽隔离）的元件隔离区域中，每个元件区域包括：一个通道区域形成为在水平方向夹着沟道区的源/漏区; 形成在通道区域上并且鸟嘴的角度为1度或更小的栅极绝缘膜，所述鸟喙从元件隔离区的与面向沟道区域的表面相对的表面形成，大致垂直于源极/漏极区域夹着沟道区域的方向的水平方向; 以及形成在栅极绝缘膜上的栅极电极层。

7. 发明授权

US06974746B2 Method of manufacturing a nonvolatile semiconductor memory device having a stacked gate structure 失效
标题翻译：具有层叠栅极结构的非易失性半导体存储器件的制造方法
公开(公告)号：US06974746B2
公开(公告)日：2005-12-13
申请号：US10716556
申请日：2003-11-20
申请人： Tadashi Iguchi , Yoshiaki Himeno , Hiroaki Tsunoda
发明人： Tadashi Iguchi , Yoshiaki Himeno , Hiroaki Tsunoda
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/66825
摘要： A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.
摘要翻译：旨在防止由浮动栅极之间的电荷的移动引起的数据破坏，从而提高可靠性的非易失性半导体存储器件包括埋入硅衬底中以隔离条形元件形成区域的元件隔离/绝缘膜。在基板上形成有通过第一栅极绝缘膜的浮动栅极，并且还经由第二栅极绝缘膜的控制栅极。源极和漏极扩散层与控制栅极自对准地形成。浮动栅极上的第二栅极绝缘膜通过在元件隔离/绝缘膜上方的狭缝与浮动栅极分开并分离成各个存储单元的离散部分。

8. 发明授权

US07586786B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07586786B2
公开(公告)日：2009-09-08
申请号：US12106953
申请日：2008-04-21
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C11/34
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.
摘要翻译：一种从非易失性半导体存储器读出数据的方法，包括对位线接触施加第一电压的步骤; 向源极线接触施加第二电压，其中所述第二电压基本上小于所述第一电压; 施加第三和第四选择栅极晶体管的第三电压栅极，所述第三电压被配置为使所述第三和第四选择栅极晶体管导通; 对第二存储单元单元的多个存储单元晶体管的栅极施加第四电压，第四电压被配置为使第二存储单元单元的多个存储单元晶体管导通，取决于存储的数据在存储单元中; 对第一存储单元单元的多个存储单元晶体管的栅极施加第五电压，第五电压被配置为使第一存储单元单元的多个存储单元晶体管导通; 其中所述第五电压大于所述第四电压。

9. 发明申请

US20060244098A1 Semiconductor device and method of manufacturing a semiconductor device 审中-公开
公开(公告)号：US20060244098A1
公开(公告)日：2006-11-02
申请号：US11477382
申请日：2006-06-30
申请人： Tadashi Iguchi , Hiroaki Tsunoda , Koichi Matsuno
发明人： Tadashi Iguchi , Hiroaki Tsunoda , Koichi Matsuno
IPC分类号： H01L29/00
CPC分类号： H01L21/28123 , H01L21/28247 , H01L21/76224 , H01L21/76232
摘要： A semiconductor device comprises a semiconductor substrate having a substrate top surface on which a device should be formed; a gate electrode having an opposed surface opposed to said substrate top surface, and electrically insulated from said semiconductor substrate by a gate insulating film, a trench formed through said gate electrode into said semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of said substrate top surface, a first boundary end portion, which is defined between a substrate side surface of said semiconductor substrate forming a part of the side surface of said trench and said substrate top surface, and a second boundary end portion, which is defined between a gate side surface of said gate electrode forming another part of the side surface of said trench and said opposed surface, wherein said first boundary end portion and said second boundary end portion have spherical shapes having a curvature radius not smaller than 30 angstrom.

10. 发明申请

US20050116304A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050116304A1
公开(公告)日：2005-06-02
申请号：US11031044
申请日：2005-01-10
申请人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
发明人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L21/336
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.
摘要翻译：在包括多个元件区域的半导体器件和基于将元件区域彼此电隔离的STI（浅沟槽隔离）的元件隔离区域中，每个元件区域包括：一个通道区域形成为在水平方向夹着沟道区的源/漏区; 形成在通道区域上并且鸟嘴的角度为1度或更小的栅极绝缘膜，所述鸟喙从元件隔离区的与面向沟道区域的表面相对的表面形成，大致垂直于源极/漏极区域夹着沟道区域的方向的水平方向; 以及形成在栅极绝缘膜上的栅极电极层。

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