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1. 发明授权

US06933194B2 Method of manufacturing semiconductor device using STI technique 失效
标题翻译：使用STI技术制造半导体器件的方法
公开(公告)号：US06933194B2
公开(公告)日：2005-08-23
申请号：US10670249
申请日：2003-09-26
申请人： Kazuhito Narita , Eiji Sakagami , Hiroaki Tsunoda , Masahisa Sonoda , Hideyuki Kobayashi
发明人： Kazuhito Narita , Eiji Sakagami , Hiroaki Tsunoda , Masahisa Sonoda , Hideyuki Kobayashi
IPC分类号： H01L21/28 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/76224 , H01L21/823481 , H01L27/115
摘要： A method of manufacturing a semiconductor device including forming a laminate structure which includes a gate insulation film on a semiconductor substrate and a gate electrode material film on the gate insulation film, processing the gate electrode material film to obtain a gate electrode having a reverse tapered cross section, and forming a device isolation insulation film in direct contact with a side surface of the gate electrode.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成包括栅极绝缘膜的层叠结构和栅极绝缘膜上的栅电极材料膜，处理栅电极材料膜以获得具有反向锥形交叉的栅电极并且形成与栅电极的侧表面直接接触的器件隔离绝缘膜。

2. 发明授权

US06642568B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06642568B2
公开(公告)日：2003-11-04
申请号：US09892487
申请日：2001-06-28
申请人： Kazuhito Narita , Eiji Sakagami , Hiroaki Tsunoda , Masahisa Sonoda , Hideyuki Kobayashi
发明人： Kazuhito Narita , Eiji Sakagami , Hiroaki Tsunoda , Masahisa Sonoda , Hideyuki Kobayashi
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L21/76224 , H01L21/823481 , H01L27/115
摘要： This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.

3. 发明授权

US06462373B2 Nonvolatile semiconductor memory device having tapered portion on side wall of charge accumulation layer 失效
标题翻译：非易失性半导体存储器件在电荷累积层的侧壁上具有锥形部分
公开(公告)号：US06462373B2
公开(公告)日：2002-10-08
申请号：US09725564
申请日：2000-11-30
申请人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
发明人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.
摘要翻译：在非易失性半导体存储器件中，在相邻的两个器件隔离区域之间形成电荷累积层，夹在器件隔离区域的电荷累积层的至少一部分具有各自具有80度以上的锥角的侧壁使得下端的电荷累积层的宽度比上端的宽度宽，器件隔离区域的开口尺寸为0.25μm以下，存储单元的栅极长度为0.2μm以下。

4. 发明授权

US08259494B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
公开(公告)号：US08259494B2
公开(公告)日：2012-09-04
申请号：US12855507
申请日：2010-08-12
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

5. 发明申请

US20060120130A1 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US20060120130A1
公开(公告)日：2006-06-08
申请号：US11330352
申请日：2006-01-12
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
摘要翻译：提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部并且将第二块布置在其另一部分上。存储单元阵列的端侧上的第一存储单元单元的结构与第二存储单元单元的结构不同。用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

6. 发明授权

US06340611B1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06340611B1
公开(公告)日：2002-01-22
申请号：US09628278
申请日：2000-07-28
申请人： Kazuhiro Shimizu , Seiichi Aritome , Toshiharu Watanabe , Kazuhito Narita
发明人： Kazuhiro Shimizu , Seiichi Aritome , Toshiharu Watanabe , Kazuhito Narita
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of element isolating regions.
摘要翻译：非易失性半导体存储器件包括半导体衬底，设置在半导体衬底中的元件隔离区，由元件隔离区中的两个相邻元件隔离区限定的第一元件区和形成在元件区中的存储单元晶体管，的存储单元晶体管包括形成在对应的一个元件隔离区域上的第一栅极绝缘膜，形成在栅极绝缘膜上的浮置栅电极，形成在浮置栅电极上的第二栅极绝缘膜和形成的控制电极在第二栅极绝缘膜上并且共同连接到特定数量的存储单元晶体管中以用作字线，并且浮置栅极包括第一导电构件，其侧面与两个相邻侧的端部接触和与第一导电膜电连接的第二导电部件并且形成为跨越两个相邻的元件隔离区域之间的间隙。

7. 发明申请

US20100309723A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD 有权
公开(公告)号：US20100309723A1
公开(公告)日：2010-12-09
申请号：US12855507
申请日：2010-08-12
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

8. 发明授权

US07787277B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US07787277B2
公开(公告)日：2010-08-31
申请号：US12052882
申请日：2008-03-21
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
摘要翻译：提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部并且将第二块布置在其另一部分上。存储单元阵列的端侧上的第一存储单元单元的结构与第二存储单元单元的结构不同。用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

9. 发明申请

US20070190727A1 Nonvolatile semiconductor memory device and manufacturing method therefor 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070190727A1
公开(公告)日：2007-08-16
申请号：US11783368
申请日：2007-04-09
申请人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
发明人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7881
摘要： A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.
摘要翻译：一种制造在外围电路中包括至少一个MOS晶体管的非易失性半导体存储器件的方法，还包括在半导体衬底中形成用于存储单元的第一阱和用于MOS晶体管的第二阱。

10. 发明授权

US06836444B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US06836444B2
公开(公告)日：2004-12-28
申请号：US10452128
申请日：2003-06-03
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C1100
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes a memory cell array comprising memory cell units arranged in an array form, first blocks including first memory cell units each having at least one memory cell and at least one selection gate transistor, and second blocks including second memory cell units each having at least one memory cell and at least one selection gate transistor, wherein the first blocks are arranged on both end portions of the memory cell array, the second blocks are arranged in another portion, and a structure of the first memory cell units on the end portions of the memory cell array is different from a structure of the second memory cell units.
摘要翻译：半导体存储器件包括存储单元阵列，其包括以阵列形式布置的存储单元单元，第一块包括每个具有至少一个存储单元和至少一个选择栅极晶体管的第一存储单元单元，以及包括第二存储单元单元的第二块具有至少一个存储单元和至少一个选择栅晶体管，其中所述第一块布置在所述存储单元阵列的两端部分上，所述第二块布置在另一部分中，并且所述第一存储单元单元的结构存储单元阵列的端部与第二存储单元单元的结构不同。

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