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1. 发明授权

US07795667B2 Semiconductor memory preventing an electric short circuit between a word line and a semiconductor substrate, and manufacturing method for the semiconductor memory 失效
标题翻译：防止字线和半导体基板之间的电短路的半导体存储器以及半导体存储器的制造方法
公开(公告)号：US07795667B2
公开(公告)日：2010-09-14
申请号：US10612033
申请日：2003-07-03
申请人： Tadashi Iguchi , Katsuhiro Ishida , Hiroaki Tsunoda , Hirohisa Iizuka , Hiroaki Hazama , Seiichi Mori
发明人： Tadashi Iguchi , Katsuhiro Ishida , Hiroaki Tsunoda , Hirohisa Iizuka , Hiroaki Hazama , Seiichi Mori
IPC分类号： H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.
摘要翻译：半导体器件包括非易失性存储器，其包括存储单元阵列，元件隔离区，第二沟槽和字线。存储单元阵列由具有浮置电极且在半导体衬底上以矩阵形状排列的存储单元构成。每个元件隔离区域具有形成在半导体衬底中的第一沟槽和沿着栅极宽度方向彼此相邻的存储单元和填充在第一沟槽中的隔离填料。第二沟槽形成在隔离填料中并且沿着栅极宽度方向彼此相邻的存储单元的浮置电极之间，并且在其底部处窄。字线连接到存储单元，埋在第二沟槽中并沿着栅极宽度方向延伸。

2. 发明申请

US20070190727A1 Nonvolatile semiconductor memory device and manufacturing method therefor 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070190727A1
公开(公告)日：2007-08-16
申请号：US11783368
申请日：2007-04-09
申请人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
发明人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7881
摘要： A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.
摘要翻译：一种制造在外围电路中包括至少一个MOS晶体管的非易失性半导体存储器件的方法，还包括在半导体衬底中形成用于存储单元的第一阱和用于MOS晶体管的第二阱。

3. 发明授权

US06462373B2 Nonvolatile semiconductor memory device having tapered portion on side wall of charge accumulation layer 失效
标题翻译：非易失性半导体存储器件在电荷累积层的侧壁上具有锥形部分
公开(公告)号：US06462373B2
公开(公告)日：2002-10-08
申请号：US09725564
申请日：2000-11-30
申请人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
发明人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.
摘要翻译：在非易失性半导体存储器件中，在相邻的两个器件隔离区域之间形成电荷累积层，夹在器件隔离区域的电荷累积层的至少一部分具有各自具有80度以上的锥角的侧壁使得下端的电荷累积层的宽度比上端的宽度宽，器件隔离区域的开口尺寸为0.25μm以下，存储单元的栅极长度为0.2μm以下。

4. 发明授权

US07238975B2 Nonvolatile semiconductor memory device and manufacturing method therefor 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07238975B2
公开(公告)日：2007-07-03
申请号：US10860014
申请日：2004-06-04
申请人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
发明人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7881
摘要： A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.
摘要翻译：包括外围电路中的至少一个MOS晶体管的非易失性半导体存储器件包括半导体衬底，用于限定多个元件形成区域的隔离绝缘膜，每个隔离绝缘膜被掩埋在设置在半导体衬底中的隔离沟槽中，经由第一栅极绝缘膜设置在每个元件形成区域中的浮动栅极，经由第二栅极绝缘膜设置在浮置栅极上的控制栅极，以及设置在半导体衬底中的与控制器自对准的源极和漏极区域栅极，其中所述浮置栅极在沟道宽度方向上的隔离端处自对准，并且包括多个多晶硅膜。

5. 发明申请

US20050012142A1 Nonvolatile semiconductor memory device and manufacturing method therefor 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20050012142A1
公开(公告)日：2005-01-20
申请号：US10860014
申请日：2004-06-04
申请人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
发明人： Hiroaki Hazama , Seiichi Mori , Hirohisa Iizuka , Norio Ootani , Kazuhito Narita
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7881
摘要： A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.
摘要翻译：包括外围电路中的至少一个MOS晶体管的非易失性半导体存储器件包括半导体衬底，用于限定多个元件形成区域的隔离绝缘膜，每个隔离绝缘膜被掩埋在设置在半导体衬底中的隔离沟槽中，经由第一栅极绝缘膜设置在每个元件形成区域中的浮动栅极，经由第二栅极绝缘膜设置在浮置栅极上的控制栅极，以及设置在半导体衬底中的与控制器自对准的源极和漏极区域栅极，其中所述浮置栅极在沟道宽度方向上的隔离端处自对准，并且包括多个多晶硅膜。

6. 发明申请

US20060157801A1 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060157801A1
公开(公告)日：2006-07-20
申请号：US11302203
申请日：2005-12-14
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
摘要翻译：一种非易失性半导体存储器件的制造方法，具有在存储单元部分的外围电路部分和第二栅电极上形成第一栅电极的步骤，将杂质引入外围电路部分和存储单元部分的步骤，在至少所述存储单元部分之上形成第一绝缘膜的步骤，以及对其中引入了所述杂质的所述半导体衬底进行退火的步骤。第一栅电极具有第一栅极长度。第二栅电极具有比第一栅极长度短的第二栅极长度。

7. 发明授权

US06828624B1 Nonvolatile semiconductor memory device covered with insulating film which is hard for an oxidizing agent to pass therethrough 失效
标题翻译：被绝缘膜覆盖的非易失性半导体存储器件，其难以氧化剂通过
公开(公告)号：US06828624B1
公开(公告)日：2004-12-07
申请号：US09556777
申请日：2000-04-25
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A nonvolatile semiconductor memory device includes comprises: an element isolation region being in contact with a first element region, an insulating film covering a memory cell, a peripheral transistor and the element isolation region, an inter-level insulating film provided on the surface of the insulating film, and a contact hole provided in the inter-level insulating film and the insulating film. The inter-level insulating film contains an insulator different from the insulating film. The contact hole reaches at least one of source and drain diffusion layers of the memory cell and overlaps the element isolation region. The insulating film contains an insulator different from the element isolation region and the insulating film is harder for an oxidizing agent to pass therethrough than a silicon oxide film. A surface of the insulating film is oxidized.
摘要翻译：非易失性半导体存储器件包括：与第一元件区域接触的元件隔离区域，覆盖存储单元的绝缘膜，外围晶体管和元件隔离区域，设置在第一元件区域的表面上的层间绝缘膜绝缘膜和设置在层间绝缘膜和绝缘膜中的接触孔。层间绝缘膜含有与绝缘膜不同的绝缘体。接触孔到达存储单元的源极和漏极扩散层中的至少一个并且与元件隔离区域重叠。绝缘膜含有与元件隔离区不同的绝缘体，绝缘膜比氧化硅膜更难以通过氧化剂。绝缘膜的表面被氧化。

8. 发明授权

US06747311B2 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06747311B2
公开(公告)日：2004-06-08
申请号：US10145122
申请日：2002-05-15
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A nonvolatile semiconductor memory device includes memory cell transistors, peripheral transistors, first post-oxidation films provided on the gate electrode of all of the memory cell transistors, second post-oxidation films provided on the gate electrode of all of the peripheral transistors, first insulating films provided on the first post-oxidation films and covering a side surface of the gate electrode of all of the memory cell transistors and second insulating films provided on the second post-oxidation films and covering a side surface of the gate electrode of all of the peripheral transistors. The first and second insulating films are harder for an oxidizing agent to pass therethrough than a silicon oxide film, and the first and second insulating films are oxidized.
摘要翻译：非易失性半导体存储器件包括存储单元晶体管，外围晶体管，设置在所有存储单元晶体管的栅电极上的第一后氧化膜，设置在所有外围晶体管的栅电极上的第二后氧化膜，第一绝缘提供在第一后氧化膜上并覆盖所有存储单元晶体管的栅电极的侧表面的膜和设置在第二后氧化膜上的第二绝缘膜，并覆盖所有栅极电极的侧表面外围晶体管。第一绝缘膜和第二绝缘膜比氧化硅膜更难以通过氧化剂，并且第一和第二绝缘膜被氧化。

9. 发明授权

US07297599B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07297599B2
公开(公告)日：2007-11-20
申请号：US11219752
申请日：2005-09-07
申请人： Norio Ohtani , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Eiji Kamiya
发明人： Norio Ohtani , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Eiji Kamiya
IPC分类号： H01L21/8234
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成栅电极，栅极绝缘膜插入在衬底和电极之间，形成用于元件隔离的绝缘膜，从半导体衬底的表面突出，形成氧化膜在已经形成有栅电极和元件隔离绝缘膜的半导体衬底的表面上，在使用用于去除氧化膜的抗蚀剂图案的同时，在要形成自对准接触孔的区域中除去氧化膜形成在其中形成自对准接触孔的区域中，并且蚀刻从半导体衬底的表面突出的元件隔离绝缘膜的一部分，使得所述部分基本上与半导体衬底的表面成一定水平，同时使用抗蚀剂图案去除形成在自对准接触区域中的氧化膜形成孔。

10. 发明申请

US20050253202A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050253202A1
公开(公告)日：2005-11-17
申请号：US11126285
申请日：2005-05-11
申请人： Eiji Kamiya , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Norio Ohtani
发明人： Eiji Kamiya , Hirohisa Iizuka , Hiroaki Hazama , Kazuhito Narita , Norio Ohtani
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/04 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76897 , H01L21/26586 , H01L21/76802 , H01L21/76834 , H01L27/10873 , H01L27/10894
摘要： A semiconductor device includes a semiconductor substrate, a plurality of memory cell transistors and select gate transistors both formed in a memory cell region of the semiconductor substrate, and a transistor formed in a peripheral circuit region of the substrate and having a high breakdown voltage. Each select gate transistor of the memory cell region has a gate electrode under which an ion implanted layer is formed for adjustment of a threshold. The transistor having the high breakdown voltage includes a contact region around which a gate insulation film remains.
摘要翻译：半导体器件包括形成在半导体衬底的存储单元区域中的半导体衬底，多个存储单元晶体管和选择栅极晶体管，以及形成在衬底的外围电路区域中且具有高击穿电压的晶体管。存储单元区域的每个选择栅极晶体管具有栅电极，在该栅电极处形成用于调整阈值的离子注入层。具有高击穿电压的晶体管包括保持栅极绝缘膜的接触区域。

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