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1. 发明申请

US20060018181A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20060018181A1
公开(公告)日：2006-01-26
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C8/00
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

2. 发明授权

US07586786B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07586786B2
公开(公告)日：2009-09-08
申请号：US12106953
申请日：2008-04-21
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C11/34
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.
摘要翻译：一种从非易失性半导体存储器读出数据的方法，包括对位线接触施加第一电压的步骤; 向源极线接触施加第二电压，其中所述第二电压基本上小于所述第一电压; 施加第三和第四选择栅极晶体管的第三电压栅极，所述第三电压被配置为使所述第三和第四选择栅极晶体管导通; 对第二存储单元单元的多个存储单元晶体管的栅极施加第四电压，第四电压被配置为使第二存储单元单元的多个存储单元晶体管导通，取决于存储的数据在存储单元中; 对第一存储单元单元的多个存储单元晶体管的栅极施加第五电压，第五电压被配置为使第一存储单元单元的多个存储单元晶体管导通; 其中所述第五电压大于所述第四电压。

3. 发明授权

US07382649B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07382649B2
公开(公告)日：2008-06-03
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C11/34
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

4. 发明申请

US20090016108A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20090016108A1
公开(公告)日：2009-01-15
申请号：US12106953
申请日：2008-04-21
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.
摘要翻译：一种从非易失性半导体存储器读出数据的方法，包括对位线接触施加第一电压的步骤; 向源极线接触施加第二电压，其中所述第二电压基本上小于所述第一电压; 施加第三和第四选择栅极晶体管的第三电压栅极，所述第三电压被配置为使所述第三和第四选择栅极晶体管导通; 对第二存储单元单元的多个存储单元晶体管的栅极施加第四电压，第四电压被配置为使第二存储单元单元的多个存储单元晶体管导通，取决于存储的数据在存储单元中; 对第一存储单元单元的多个存储单元晶体管的栅极施加第五电压，第五电压被配置为使第一存储单元单元的多个存储单元晶体管导通; 其中所述第五电压大于所述第四电压。

5. 发明申请

US20070293018A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH SHALLOW TRENCH ISOLATION 审中-公开
标题翻译：制备半导体器件的方法
公开(公告)号：US20070293018A1
公开(公告)日：2007-12-20
申请号：US11837915
申请日：2007-08-13
申请人： Ryuichi KAMO , Hisashi Watanobe , Tadashi Iguchi
发明人： Ryuichi KAMO , Hisashi Watanobe , Tadashi Iguchi
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L27/115 , H01L27/11521
摘要： In fabrication of a semiconductor device, a first insulating film, electrode film and silicon nitride film sequentially stacked on a semiconductor substrate are etched with the substrate so that a trench is formed. The electrode film is then exposed. A second insulating film buried in the trench is isotropically etched so that an upper side wall of the electrode film is exposed, so that a side end of an upper surface of the insulating film is located between the upper surfaces of the substrate and electrode film and so that a middle upper portion of an upper surface of the second insulating film is higher than the side end and lower than the upper surface of the first electrode film, A third insulating film is formed on the upper surface of the first electrode film so as to entirely cover the upper surface of the second insulating film.
摘要翻译：在半导体器件的制造中，用衬底蚀刻顺序层叠在半导体衬底上的第一绝缘膜，电极膜和氮化硅膜，从而形成沟槽。然后暴露电极膜。埋入沟槽中的第二绝缘膜被各向同性蚀刻，使得电极膜的上侧壁露出，使得绝缘膜的上表面的侧端位于基板和电极膜的上表面之间，使得第二绝缘膜的上表面的中间上部高于第一电极膜的侧端并且低于第一电极膜的上表面。在第一电极膜的上表面上形成第三绝缘膜，从而以完全覆盖第二绝缘膜的上表面。

6. 发明申请

US20050221578A1 Semiconductor device with shallow trench isolation and method of fabricating the same 失效
标题翻译：具有浅沟槽隔离的半导体器件及其制造方法
公开(公告)号：US20050221578A1
公开(公告)日：2005-10-06
申请号：US11060542
申请日：2005-02-18
申请人： Ryuichi Kamo , Hisashi Watanobe , Tadashi Iguchi
发明人： Ryuichi Kamo , Hisashi Watanobe , Tadashi Iguchi
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L29/00 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76224 , H01L27/115 , H01L27/11521
摘要： A semiconductor device includes a semiconductor substrate having an upper surface, a trench formed in the semiconductor substrate, a first insulating film formed on the semiconductor substrate so as to be located at opposite sides of the trench, a polycrystalline silicon film stacked on the first insulating film, the polycrystalline silicon film having an upper surface, a second insulating film buried in the trench and having an upper surface end located lower than the upper surface of the polycrystalline silicon film and higher than the upper surface of the semiconductor substrate, the second insulating film having a central upper surface located nearer to the upper surface of the polycrystalline silicon film than the upper surface end thereof.
摘要翻译：半导体器件包括具有上表面的半导体衬底，形成在半导体衬底中的沟槽，形成在半导体衬底上以便位于沟槽的相对侧的第一绝缘膜，堆叠在第一绝缘层上的多晶硅膜膜，具有上表面的多晶硅膜，埋在沟槽中的第二绝缘膜，具有位于比多晶硅膜的上表面低的上表面端，并且高于半导体衬底的上表面，第二绝缘体膜的中央上表面比其上表面端更靠近多晶硅膜的上表面。

7. 发明授权

US07276757B2 Semiconductor device with shallow trench isolation and method of fabricating the same 失效
标题翻译：具有浅沟槽隔离的半导体器件及其制造方法
公开(公告)号：US07276757B2
公开(公告)日：2007-10-02
申请号：US11060542
申请日：2005-02-18
申请人： Ryuichi Kamo , Hisashi Watanobe , Tadashi Iguchi
发明人： Ryuichi Kamo , Hisashi Watanobe , Tadashi Iguchi
IPC分类号： H01L29/788
CPC分类号： H01L21/76224 , H01L27/115 , H01L27/11521
摘要： A semiconductor device includes a semiconductor substrate including a first upper surface, a first insulating film including an upper portion including a first side wall having a first upper end and a second upper surface having a second upper end, a second insulating film formed on the first upper surface of the substrate, a floating gate electrode including a third upper surface, a second side wall and a lower surface, a third insulating film, and a control gate electrode. A height of the second upper end is lower than a height of the third upper surface and higher than a height of the first upper end relative to the first upper surface. The first upper end is located at a position higher than the lower surface of the floating gate electrode. The entire second side wall is aligned with the first side wall of the first insulating film.
摘要翻译：半导体器件包括：半导体衬底，包括第一上表面;第一绝缘膜，其包括上部，该上部包括具有第一上端的第一侧壁和具有第二上端的第二上表面;第二绝缘膜，基板的上表面，包括第三上表面，第二侧壁和下表面的浮栅，第三绝缘膜和控制栅电极。第二上端的高度低于第三上表面的高度，并且高于第一上端相对于第一上表面的高度。第一上端位于高于浮栅电极的下表面的位置。整个第二侧壁与第一绝缘膜的第一侧壁对齐。

8. 发明授权

US07795667B2 Semiconductor memory preventing an electric short circuit between a word line and a semiconductor substrate, and manufacturing method for the semiconductor memory 失效
标题翻译：防止字线和半导体基板之间的电短路的半导体存储器以及半导体存储器的制造方法
公开(公告)号：US07795667B2
公开(公告)日：2010-09-14
申请号：US10612033
申请日：2003-07-03
申请人： Tadashi Iguchi , Katsuhiro Ishida , Hiroaki Tsunoda , Hirohisa Iizuka , Hiroaki Hazama , Seiichi Mori
发明人： Tadashi Iguchi , Katsuhiro Ishida , Hiroaki Tsunoda , Hirohisa Iizuka , Hiroaki Hazama , Seiichi Mori
IPC分类号： H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.
摘要翻译：半导体器件包括非易失性存储器，其包括存储单元阵列，元件隔离区，第二沟槽和字线。存储单元阵列由具有浮置电极且在半导体衬底上以矩阵形状排列的存储单元构成。每个元件隔离区域具有形成在半导体衬底中的第一沟槽和沿着栅极宽度方向彼此相邻的存储单元和填充在第一沟槽中的隔离填料。第二沟槽形成在隔离填料中并且沿着栅极宽度方向彼此相邻的存储单元的浮置电极之间，并且在其底部处窄。字线连接到存储单元，埋在第二沟槽中并沿着栅极宽度方向延伸。

9. 发明申请

US20070278562A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD 失效
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：US20070278562A1
公开(公告)日：2007-12-06
申请号：US11833276
申请日：2007-08-03
申请人： Tadashi Iguchi , Yoshiaki Himeno , Hiroaki Tsunoda
发明人： Tadashi Iguchi , Yoshiaki Himeno , Hiroaki Tsunoda
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/66825
摘要： A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.
摘要翻译：旨在防止由浮动栅极之间的电荷的移动引起的数据破坏，从而提高可靠性的非易失性半导体存储器件包括埋入硅衬底中以隔离条形元件形成区域的元件隔离/绝缘膜。经由第一栅极绝缘膜形成在衬底区域浮动栅极上，并且还经由第二栅极绝缘膜形成控制栅极。源极和漏极扩散层与控制栅极自对准地形成。浮动栅极上的第二栅极绝缘膜通过在元件隔离/绝缘膜上方的狭缝与浮动栅极分开并分离成各个存储单元的离散部分。

10. 发明授权

US06984858B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06984858B2
公开(公告)日：2006-01-10
申请号：US10293254
申请日：2002-11-14
申请人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
发明人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
IPC分类号： H01L27/108
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.
摘要翻译：在包括多个元件区域的半导体器件和基于将元件区域彼此电隔离的STI（浅沟槽隔离）的元件隔离区域中，每个元件区域包括：一个通道区域形成为在水平方向夹着沟道区的源/漏区; 形成在通道区域上并且鸟嘴的角度为1度或更小的栅极绝缘膜，所述鸟喙从元件隔离区的与面向沟道区域的表面相对的表面形成，大致垂直于源极/漏极区域夹着沟道区域的方向的水平方向; 以及形成在栅极绝缘膜上的栅极电极层。

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