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    • 1. 发明授权
    • Radio communication system, base station apparatus, radio resource control method, and non-transitory computer readable medium
    • 无线电通信系统,基站装置,无线电资源控制方法和非暂时计算机可读介质
    • US08619680B2
    • 2013-12-31
    • US13366032
    • 2012-02-03
    • Motoki MoritaYasuhiko Matsunaga
    • Motoki MoritaYasuhiko Matsunaga
    • H04Q7/00H04J3/16
    • H04W72/082H04W16/10H04W52/244H04W84/045H04W88/08
    • A base station includes a radio communication unit, a resource adjustment unit, a resource division unit and a detection unit. The resource adjustment unit determines radio resources to be allocated to a downlink communication from a radio resource region shared with another base station. The resource division unit limits, to a first radio resource segment which is a part of the radio resource region, radio resources in response to estimating that communication quality of the downlink communication using the limited first radio resource segment is improved over the communication quality of the first downlink communication when using the entire range of the radio resource region that is shared with the other base station. The detection unit detects execution of resource division by the other base station for limiting radio resources used for another downlink communication between the other base station and a mobile station to a second radio resource segment.
    • 基站包括无线电通信单元,资源调整单元,资源划分单元和检测单元。 资源调整单元从与另一基站共享的无线资源区域确定要分配给下行链路通信的无线资源。 所述资源分割单元对作为所述无线资源区域的一部分的第一无线资源段限制无线资源,所述无线资源响应于使用所述受限的第一无线资源段的所述下行通信的通信质量相对于 当使用与另一个基站共享的无线电资源区域的整个范围时的第一下行链路通信。 检测单元检测另一基站的资源划分的执行,用于将用于另一基站与移动台之间的另一下行链路通信的无线资源限制到第二无线电资源段。
    • 6. 发明授权
    • Semiconductor memory device and manufacturing method thereof
    • 半导体存储器件及其制造方法
    • US08098527B2
    • 2012-01-17
    • US12649822
    • 2009-12-30
    • Koichi FukudaDai NakamuraYasuhiko Matsunaga
    • Koichi FukudaDai NakamuraYasuhiko Matsunaga
    • G11C11/34
    • H01L27/11519G11C16/0483H01L27/0207H01L27/11521H01L27/11526H01L27/11529
    • A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval.
    • 半导体存储器件包括半导体衬底; 所述存储单元阵列包括能够电存储数据的多个存储单元;存储单元阵列, 感测放大器,被配置为检测存储在所述存储器单元中的至少一个中的数据; 电池源驱动器,电连接到存储器单元的源极端子,并且被配置为向存储器单元的至少一个源极侧端子提供源极电位; 第一布线,被配置为电连接所述存储单元的至少一个源极端子和所述单元源驱动器; 以及形成在与所述第一布线相同的布线层中的第二布线,所述第二布线与所述第一布线绝缘并且电连接到所述读出放大器,其中所述第一布线和所述第二布线具有设置在所述第一布线的多个通孔 预定间隔。
    • 7. 发明授权
    • Communication network failure cause analysis system, failure cause analysis method, and failure cause analysis program
    • 通信网络故障原因分析系统,故障原因分析方法和故障原因分析程序
    • US08095819B2
    • 2012-01-10
    • US12663180
    • 2008-06-06
    • Yoshinori WatanabeYasuhiko Matsunaga
    • Yoshinori WatanabeYasuhiko Matsunaga
    • G06F11/00
    • H04M3/2254G06F11/0709G06F11/079H04L41/0631
    • A failure cause analysis system for estimating a cause of a failure in a communication network from recorded contents of internal processing of a communication apparatus includes: feature extraction means for extracting a statistical feature of the recorded contents at a time of occurrence of a failure; and failure cause estimation means for estimating a failure cause based on similarity between a statistical feature of the recorded contents that is acquired at a time of occurrence of a past failure with a known failure cause and the statistical feature of the recorded contents that is acquired at the time of occurrence of the failure. The failure cause analysis system of a communication network provided can acquire the correspondence between failure features and failure causes from past failure cases irrespective of the number of cases as to communication network failures that are detected from process logs retained in communication apparatuses, and quantitatively incorporate the range of dispersion of the features into a judgment to estimate the cause of occurrence of a failure.
    • 用于从通信设备的内部处理的记录内容中估计通信网络中的故障原因的故障原因分析系统包括:特征提取装置,用于在故障发生时提取记录内容的统计特征; 以及故障原因估计装置,用于基于在过去故障发生时获取的所记录内容的统计特征与已知故障原因与所获取的记录内容的统计特征之间的相似度来估计故障原因 发生故障的时间。 所提供的通信网络的故障原因分析系统可以获得来自过去故障情况的故障特征和故障原因之间的对应关系,而不管从通信设备中保留的进程日志中检测到的通信网络故障的数量,并定量地并入 将特征的分散范围判断为发生故障的原因。
    • 10. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME
    • 非易失性半导体存储器及其制造方法
    • US20100173471A1
    • 2010-07-08
    • US12720062
    • 2010-03-09
    • Kikuko SugimaeMasayuki IchigeFumitaka AraiYasuhiko MatsunagaAtsuhiro Sato
    • Kikuko SugimaeMasayuki IchigeFumitaka AraiYasuhiko MatsunagaAtsuhiro Sato
    • H01L21/336H01L21/762
    • H01L27/115G11C16/0416G11C16/0433G11C16/0483G11C16/30H01L27/11521H01L27/11524
    • A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.
    • 非易失性半导体存储器包括:存储单元晶体管,包括形成在第一隧道绝缘膜上的第一浮栅电极层,第一栅间绝缘膜,第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层,具有孔径的第二栅极间绝缘膜,第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层,具有孔的第三栅间绝缘膜,第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域,低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。