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    • 4. 发明授权
    • Remote operation apparatus of working machine
    • 工作机远程操作装置
    • US08922343B2
    • 2014-12-30
    • US12775722
    • 2010-05-07
    • Toshinori InagawaToshikazu Nakamura
    • Toshinori InagawaToshikazu Nakamura
    • G08C19/16G08C17/00
    • G08C17/00G08C2201/10G08C2201/12G08C2201/50
    • In a remote operation apparatus of a working machine including a working machine side transmission/reception unit (21) and a radio remote operation means (3) having a remote control side transmission/reception unit (31), an ON/OFF control circuit (32) for controlling the operation/non-operation state of the remote control side transmission/reception unit (31) is disposed to the radio remote operation means (3), and the working machine side transmission/reception unit (21) is called when the remote control side transmission/reception unit (31) is in an operating state by that the ON/OFF control circuit (32) is turned on, and the data showing the driving state of the working machine (1) is transmitted from the working machine side transmission/reception unit (21) to the remote control side transmission/reception unit (31) to thereby reduce an electric power consumption amount on the radio remote operation means (3).
    • 在具有工作机侧发送接收单元(21)的工作机的远程操作装置和具有遥控侧发送接收单元(31)的无线遥控单元(3)的ON / OFF控制电路( 32)用于控制遥控器侧发送/接收单元(31)的操作/非操作状态设置在无线电远程操作装置(3)上,并且当工作机侧发送/接收单元(21)被调用时 远程控制侧发送/接收单元(31)处于操作状态,ON / OFF控制电路(32)接通,并且显示工作机(1)的驱动状态的数据从工作 机侧发送接收部(21)发送到遥控侧发送接收部(31),能够减少无线遥控装置(3)的电力消耗量。
    • 6. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US07827463B2
    • 2010-11-02
    • US11270533
    • 2005-11-10
    • Shuzo OtsukaKuninori KawabataToshikazu NakamuraAkira Kikutake
    • Shuzo OtsukaKuninori KawabataToshikazu NakamuraAkira Kikutake
    • H03M13/00
    • G06F11/1032G11C7/1006G11C7/1027
    • In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.
    • 在具有纠错功能的半导体存储器件中,保持一组数据位的一部分和基于该数据位组的一组奇偶校验位,其中数据位集合和 奇偶校验位构成用于纠错的代码,并且在突发写入操作中以前导写入周期写入存储器单元。 基于数据位组和/或奇偶校验位集合的部分,在最终写入周期中更新写入存储器单元中的前导写周期中的奇偶校验位集合,以及另一组数据位 在上一部分写入前导写周期的地址处的存储单元中写入最终写周期。
    • 8. 发明授权
    • Memory with word-line driver circuit having leakage prevention transistor
    • 具有防漏晶体管的字线驱动电路的存储器
    • US07577054B2
    • 2009-08-18
    • US11979237
    • 2007-10-31
    • Toshikazu Nakamura
    • Toshikazu Nakamura
    • G11C8/00
    • G11C8/08G11C11/4085G11C11/4087G11C29/02G11C29/021G11C29/028G11C2029/1202
    • In a semiconductor memory having a plurality of word lines and bit lines and memory cells arranged at the positions of intersection thereof, a word driver circuit that drives the word line has a drive PMOS transistor and drive NMOS transistor which are connected in series between a first node and a second node and each of which has a gate connected to a third node, the word line being connected to a connection node of the two transistors. A first voltage or a second voltage lower than the first voltage is then applied to the third node, and the first voltage or second voltage is applied to the first node. In addition, between the third node and the gate of the drive PMOS transistor, there is provided a leakage prevention NMOS transistor having a gate applied with the first voltage or a voltage in the vicinity thereof.
    • 在具有布置在其相交位置处的多个字线和位线和存储单元的半导体存储器中,驱动字线的字驱动电路具有驱动PMOS晶体管和驱动NMOS晶体管,其串联连接在第一 节点和第二节点,并且每个节点具有连接到第三节点的栅极,所述字线连接到所述两个晶体管的连接节点。 然后将第一电压或低于第一电压的第二电压施加到第三节点,并且将第一电压或第二电压施加到第一节点。 此外,在驱动PMOS晶体管的第三节点和栅极之间,提供了具有施加有第一电压的栅极或其附近的电压的防漏NMOS晶体管。