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1. 发明授权

US11721372B2 System and method for reading and writing memory management data through a non-volatile cell based register 有权
公开(公告)号：US11721372B2
公开(公告)日：2023-08-08
申请号：US17895565
申请日：2022-08-25
申请人： Micron Technology, Inc.
发明人： Yasushi Matsubara , Yusuke Jono , Donald Martin Morgan , Nobuo Yamamoto
IPC分类号： G11C7/20 , G11C11/22 , G11C7/06 , G11C7/10 , G11C7/18
CPC分类号： G11C7/065 , G11C7/1027 , G11C7/1039 , G11C7/18 , G11C7/20
摘要： Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

2. 发明授权

US09640245B2 Semiconductor device and operating method thereof 有权
公开(公告)号：US09640245B2
公开(公告)日：2017-05-02
申请号：US14798176
申请日：2015-07-13
申请人： SK hynix Inc.
发明人： Sun-Hye Shin , Nak-Kyu Park
IPC分类号： G11C7/10 , G11C11/408 , G11C11/4076
CPC分类号： G11C11/408 , G11C7/10 , G11C7/1027 , G11C7/1042 , G11C11/4076 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C2207/005
摘要： A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.

3. 发明授权

US09281035B2 Semiconductor integrated circuit capable of controlling read command 有权
公开(公告)号：US09281035B2
公开(公告)日：2016-03-08
申请号：US14284816
申请日：2014-05-22
申请人： SK HYNIX INC.
发明人： Kyong Ha Lee
IPC分类号： G11C7/22 , G11C7/10 , G11C8/04 , G11C8/10
CPC分类号： G11C7/222 , G11C7/1027 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C8/04 , G11C8/10
摘要： The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

4. 发明授权

US08862811B2 Semiconductor device performing burst order control and data bus inversion 有权
标题翻译：半导体器件执行突发命令控制和数据总线反转
公开(公告)号：US08862811B2
公开(公告)日：2014-10-14
申请号：US13629328
申请日：2012-09-27
申请人： Elpida Memory, Inc.
发明人： Taihei Shido , Chiaki Dono , Chikara Kondo , Shinya Miyazaki
IPC分类号： G06F12/00 , G11C7/10 , G11C11/4096
CPC分类号： G06F12/00 , G11C7/1006 , G11C7/1012 , G11C7/1027 , G11C11/4096
摘要： Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits.
摘要翻译：这里公开了一种设备，其包括分别传输多个顺序第一数据位的第一数据线，分别发送多个连续第二数据位的第二数据线的第三数据线分别发送多个连续第三数据位的装置根据地址信息，从多个第一数据线提供的多个第一数据位重新排列顺序的BOC电路，向多个第二数据线提供结果的BOC电路作为多个第二数据位，以及 DBI电路根据预定条件独立地执行从多个第二数据线提供的多个第二数据位的反转或非反转，DBI电路将结果提供给多个第三数据线作为多个的第三个数据位。

5. 发明申请

US20140126305A1 DATA CAPTURE SYSTEM AND METHOD, AND MEMORY CONTROLLERS AND DEVICES 有权
标题翻译：数据采集系统和方法，以及存储器控制器和设备
公开(公告)号：US20140126305A1
公开(公告)日：2014-05-08
申请号：US14148488
申请日：2014-01-06
申请人： Micron Technology, Inc.
发明人： HUY VO
IPC分类号： G11C7/10
CPC分类号： G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C11/406 , G11C11/4082 , G11C11/4093
摘要： Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.
摘要翻译：数据采集系统和方法的实施例可以用在各种设备中，例如在存储器控制器和存储设备中。数据采集系统和方法可以产生与第一组不同的第一组周期信号和第二组周期性信号。可以选择第一组周期信号或第二组周期信号来生成一组数据捕获信号。可以基于先前捕获的数据突发中的串行数据数字的数量来进行第一组或第二组的选择。然后可以使用数据捕获信号来捕获串行数据数字的突发。

6. 发明申请

US20130082761A1 SEMICONDUCTOR DEVICE HAVING INPUT RECEIVER CIRCUIT THAT OPERATES IN RESPONSE TO STROBE SIGNAL 有权
标题翻译：具有响应于结构信号的输入接收器电路的半导体器件
公开(公告)号：US20130082761A1
公开(公告)日：2013-04-04
申请号：US13628920
申请日：2012-09-27
申请人： ELPIDA MEMORY, INC.
发明人： Chiaki DONO , Seiji NARUI , Seiichi MARUNO
IPC分类号： H03K5/00 , H03K17/56
CPC分类号： G11C7/02 , G11C7/1027 , G11C11/4076 , G11C11/4093
摘要： Disclosed herein is a device that includes an input receiver circuit activated by a strobe signal to generate an output signal by comparing a potential of an input signal with a reference potential, and a noise canceller cancelling noise superimposed on the reference potential due to a change in the strobe signal.
摘要翻译：本文公开了一种装置，其包括由选通信号激活的输入接收器电路，以通过将输入信号的电位与参考电位进行比较来产生输出信号，以及由于改变引起的叠加在参考电位上的噪声消除器消除噪声选通信号。

7. 发明授权

US08281052B2 Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction 有权
标题翻译：通过在读取或写入事务期间将信号施加到至少一个外部引脚，动态设置双倍数据速率存储器件的突发长度
公开(公告)号：US08281052B2
公开(公告)日：2012-10-02
申请号：US13442228
申请日：2012-04-09
申请人： Christopher S. Johnson
发明人： Christopher S. Johnson
IPC分类号： G06F13/26 , G06F12/06 , G06F8/00 , G06F7/00
CPC分类号： G11C7/1045 , G11C7/1027 , G11C2207/105
摘要： A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.
摘要翻译：一种具有微处理器和双数据速率存储器件的微处理器系统，其具有适于接收寻址，数据和控制信息的独立的外部引脚组，以及适于将双数据速率存储器的突发类型设置为交错或顺序的存储器控制器通过双数据速率存储装置的外部引脚之一发送信号，使得当控制器发送读取命令时，根据突发类型集合，双倍数据速率存储装置将交织或依次输出的数据返回给内存控制器

8. 发明授权

US08156262B2 Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction 有权
标题翻译：通过在读取或写入事务期间将信号施加到至少一个外部引脚，动态设置双倍数据速率存储器件的突发长度
公开(公告)号：US08156262B2
公开(公告)日：2012-04-10
申请号：US13212731
申请日：2011-08-18
申请人： Christopher S. Johnson
发明人： Christopher S. Johnson
IPC分类号： G06F13/26 , G06F12/06 , G06F8/00 , G06F7/00
CPC分类号： G11C7/1045 , G11C7/1027 , G11C2207/105
摘要： One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
摘要翻译：使用存储器设备上的一个或多个外部控制引脚和/或寻址引脚来设置存储器件的突发长度和突发类型中的一个或两个。

9. 发明申请

US20120072649A1 NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：非易失性存储器系统，以及用于非易失性存储器系统的数据读/写方法
公开(公告)号：US20120072649A1
公开(公告)日：2012-03-22
申请号：US13235600
申请日：2011-09-19
申请人： Yasuo KUDO , Hiroshi Sukegawa , Kazuya Kawamoto
发明人： Yasuo KUDO , Hiroshi Sukegawa , Kazuya Kawamoto
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C7/1027
摘要： A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.
摘要翻译：非易失性存储器系统包括具有多个数据区域的非易失性存储器; 以及存储器控制器，用于控制对所述非易失性存储器的读取和写入操作。存储器控制器根据从主机设备馈送的命令和扇区计数和扇区地址，依次对非易失性存储器中所选数据区域内的多个扇区执行读/写操作。

10. 发明授权

US08027222B2 Burst mode control circuit 有权
标题翻译：突发模式控制电路
公开(公告)号：US08027222B2
公开(公告)日：2011-09-27
申请号：US12455727
申请日：2009-06-04
申请人： Kyong Ha Lee
发明人： Kyong Ha Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C7/1027 , G11C7/1066
摘要： A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period.
摘要翻译：突发模式控制单元包括：脉冲串周期信号产生单元，用于产生在脉冲串模式运行周期期间使能的脉冲串周期信号;脉冲串脉冲发生单元，用于产生脉冲脉冲脉冲，脉冲串脉冲产生单元在响应于读命令和写命令，脉冲串周期信号的使能周期，以及用于接收脉冲串信号和时钟信号的列存取信号产生单元，并产生一列控制数据输入和输出的列存取信号突发模式运行期间。

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