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1. 发明申请

US20110222210A1 ELECTRODE FOR CAPACITOR AND CAPACITOR 有权
标题翻译：电容器和电容器电极
公开(公告)号：US20110222210A1
公开(公告)日：2011-09-15
申请号：US13129983
申请日：2009-11-17
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01G9/012
CPC分类号： H01G9/052 , H01G9/0032 , H01G9/042 , H01G9/07
摘要： A capacitor includes a positive electrode base material, a dielectric layer, a positive electrode body, a dielectric layer, a negative electrode body, and a negative electrode base material. The positive electrode body is formed on the positive electrode base material and in part is in contact with the positive electrode base material. The positive electrode body is formed by association of a large number of metal particles, and the associated metal particles form a reticular network. The positive electrode base material and the positive electrode body (core part) are formed of a NiTi alloy containing Ni having a large work function. The dielectric layers (high-permittivity insulating film) are formed of titanium oxide. It is preferable that at least one Ni atomic layer is formed at an interface between the high-permittivity insulating film and the core part. Although the Ni atomic layer is preferably formed over the entire interface, the Ni atomic layer may be partially formed at the interface.
摘要翻译：电容器包括正极基材，电介质层，正极体，电介质层，负极体和负极基材。正极体形成在正极基材上，部分与正极基材接触。正极体通过大量金属颗粒的缔合形成，并且相关联的金属颗粒形成网状网络。正极基材和正极体（芯部）由具有大功函数的Ni的NiTi合金形成。电介质层（高电容率绝缘膜）由氧化钛形成。优选在高电容率绝缘膜和芯部之间的界面处形成至少一个Ni原子层。尽管Ni原子层优选在整个界面上形成，但Ni原子层可以部分地形成在界面处。

2. 发明申请

US20110128002A1 POLARIZED XENON GAS CONCENTRATION METHOD, POLARIZED XENON GAS MANUFACTURING SUPPLY DEVICE, AND MRI SYSTEM 有权
标题翻译：极化氙气浓度法，极化氙气制造供应装置及MRI系统
公开(公告)号：US20110128002A1
公开(公告)日：2011-06-02
申请号：US13055246
申请日：2009-07-29
申请人： Hideaki Fujiwara , Hirohiko Imai , Satoshi Iguchi , Hironobu Yoshimura , Atsuomi Kimura
发明人： Hideaki Fujiwara , Hirohiko Imai , Satoshi Iguchi , Hironobu Yoshimura , Atsuomi Kimura
IPC分类号： G01R33/28 , F25J3/00 , F25B21/00 , F25J1/00
CPC分类号： G01R33/282 , B01D7/02
摘要： The present invention relates to a polarized xenon gas manufacturing supply device that is provided with a polarization cell 6 that produces a polarized xenon gas by polarizing a mixture of xenon gas and a diluent gas that consists primarily of a high-boiling-point gas that has a boiling point higher than that of the xenon gas, and a condenser (9) that cools the mixed gas discharged from the polarization cell (6) and condenses and separates the high-boiling-point gas by using the difference in boiling points between the xenon gas and the high-boiling-point gas, wherein the supply device is constructed so as to re-vaporize the condensed liquid of the high-boiling-point gas produced by the condenser (9) and introduce it to the polarization cell (6). This polarized xenon gas manufacturing supply device makes it possible to continuously manufacture and supply highly polarized and highly concentrated xenon gas.
摘要翻译：本发明涉及一种偏振氙气制造供应装置，其具有通过偏振氙气和稀释气体的混合物产生偏振氙气的偏振电池6，该稀释气体主要由高沸点气体组成，该高沸点气体具有沸点高于氙气的沸点;以及冷凝器（9），冷凝从偏振电池（6）排出的混合气体，并通过使用高沸点气体的不同点冷凝并分离高沸点气体氙气和高沸点气体，其中供给装置被构造成使由冷凝器（9）产生的高沸点气体的冷凝液体再气化并将其引入偏振电池（6））。该极化氙气制造供给装置能够连续制造和供应高度极化和高浓度的氙气。

3. 发明申请

US20070235812A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070235812A1
公开(公告)日：2007-10-11
申请号：US11729972
申请日：2007-03-30
申请人： Hideaki Fujiwara , Kazunori Fujita , Yoshikazu Yamaoka , Hideki Mizuhara , Yasunori Inoue
发明人： Hideaki Fujiwara , Kazunori Fujita , Yoshikazu Yamaoka , Hideki Mizuhara , Yasunori Inoue
IPC分类号： H01L23/62
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/0408 , G11C2216/06 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/42348 , H01L29/6659 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device operating at low voltage is provided where a threshold voltage is controlled with ease. A semiconductor substrate is element-isolated by element isolation regions. A source region and a source region are spaced from each other on the semiconductor substrate. A gate electrode is formed between the source region and the drain by way of a gate insulator. A plurality of insulating particles are embedded in the gate electrode in a scattered manner at an interface between the gate insulator and the gate electrode, where the particles are in contact with the gate insulator.
摘要翻译：提供以低电压工作的半导体器件，其中容易地控制阈值电压。半导体衬底通过元件隔离区元件隔离。源极区域和源极区域在半导体衬底上彼此间隔开。通过栅极绝缘体在源区和漏极之间形成栅电极。多个绝缘颗粒以分散的方式嵌入在栅极绝缘体和栅电极之间的界面处，其中颗粒与栅极绝缘体接触。

4. 发明授权

US06897515B2 Semiconductor memory and semiconductor device 失效
标题翻译：半导体存储器和半导体器件
公开(公告)号：US06897515B2
公开(公告)日：2005-05-24
申请号：US09899267
申请日：2001-07-06
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , H01L29/42336 , H01L29/7883
摘要： A semiconductor memory capable of attaining a low voltage, a high-speed operation, low power consumption and a high degree of integration is obtained. This semiconductor memory comprises a floating gate electrode, a first source/drain region having a diode structure employed for controlling the potential of the floating gate electrode and a second source/drain region formed to hold a channel region between the same and the first source/drain region. Thus, when a channel of a transistor is turned on in reading, a large amount of current flows from the first source/drain region having a diode structure to a substrate, whereby high-speed reading can be implemented. Further, a negative voltage is readily applied to the first source/drain region having a diode structure, whereby a low voltage and low power consumption are attained and the scale of a step-up circuit is reduced, and hence a high degree of integration can be attained.
摘要翻译：可以获得能够实现低电压，高速运转，低功耗，高集成度的半导体存储器。该半导体存储器包括浮置栅极电极，具有用于控制浮置栅电极的电位的二极管结构的第一源极/漏极区域和形成为保持其与第一源极/漏极区域之间的沟道区域的第二源极/漏极区域，漏区。因此，当晶体管的沟道在读取时导通时，大量的电流从具有二极管结构的第一源极/漏极区流动到衬底，从而可以实现高速读取。此外，负电压容易地施加到具有二极管结构的第一源/漏区，由此获得低电压和低功耗，并且升压电路的规模减小，因此高集成度实现。

5. 发明授权

US06642571B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US06642571B2
公开(公告)日：2003-11-04
申请号：US10271556
申请日：2002-10-17
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , G11C16/0416 , G11C16/0425 , H01L21/28273 , H01L29/42324
摘要： A semiconductor memory capable of increasing the coupling ratio between a diffusion layer and a floating gate by reducing the coupling ratio between the floating gate and a control gate thereby easily performing high-speed writing with a low diffusion layer voltage is provided. This semiconductor memory comprises the floating gate, a first diffusion layer capacitively coupled with the floating gate for controlling the potential of the floating gate and the control gate arranged oppositely to the floating gate. In an erase operation, the control gate feeds a tunnel current to the floating gate in a direction substantially parallel to the main surface of a semiconductor substrate. Thus, the tunnel current can be fed by extracting carriers from the floating gate also when the control gate has no region overlapping with the upper portion of the floating gate.
摘要翻译：提供一种半导体存储器，其能够通过降低浮动栅极和控制栅极之间的耦合比来增加扩散层和浮置栅极之间的耦合比，从而容易地以低扩散层电压进行高速写入。该半导体存储器包括浮动栅极，与浮动栅极电容耦合的第一扩散层，用于控制与浮置栅极相对布置的浮置栅极和控制栅极的电位。在擦除操作中，控制栅极基本上平行于半导体衬底的主表面的方向将浮动栅极提供隧道电流。因此，当控制栅极没有与浮动栅极的上部重叠的区域时，也可以从浮置栅极提取载流子来馈送隧道电流。

6. 发明授权

US06610581B1 Method of forming isolation film in semiconductor device 有权
标题翻译：在半导体器件中形成隔离膜的方法
公开(公告)号：US06610581B1
公开(公告)日：2003-08-26
申请号：US09584850
申请日：2000-06-01
申请人： Yasuhiro Takeda , Hideaki Fujiwara
发明人： Yasuhiro Takeda , Hideaki Fujiwara
IPC分类号： H01L218238
CPC分类号： H01L21/76202 , H01L21/76205
摘要： There is disclosed a method of forming an isolation film in a semiconductor device, the method including the steps of: forming a silicon oxide film and a silicon nitride film in that order on a silicon substrate, using a resist pattern as a mask, etching the silicon nitride film and silicon oxide film, and forming trenches in the substrate. In the substrate, the respective trenches form a region in which isolation films are to be formed, and the region between the trenches forms an active region. In this case, each dimension is set so that a ratio W/t of width W to thickness t of the patterned silicon nitride film is 3.8 or more. Subsequently, by removing the resist pattern, subsequently using the silicon nitride film as the mask, and performing thermal oxidation at a temperature of 1050° C. to 1150° C. in an oxygen atmosphere, an isolation film is formed in the trench.
摘要翻译：公开了在半导体器件中形成隔离膜的方法，该方法包括以下步骤：在硅衬底上依次形成氧化硅膜和氮化硅膜，使用抗蚀剂图案作为掩模，蚀刻氮化硅膜和氧化硅膜，并在衬底中形成沟槽。在衬底中，相应的沟槽形成其中将形成隔离膜的区域，并且沟槽之间的区域形成有源区。在这种情况下，每个尺寸被设定为使得图案化氮化硅膜的宽度W与厚度t的比W / t为3.8以上。随后，通过去除抗蚀剂图案，随后使用氮化硅膜作为掩模，并且在氧气氛中在1050℃至1150℃的温度下进行热氧化，在沟槽中形成隔离膜。

7. 发明授权

US5234488A Mold additive for continuous casting of steel 失效
标题翻译：钢模连续铸模用添加剂
公开(公告)号：US5234488A
公开(公告)日：1993-08-10
申请号：US563802
申请日：1990-08-06
申请人： Kenji Ichikawa , Osamu Nomura , Akihiro Morita , Yoichiro Kawabe , Hideaki Fujiwara , Koyo Yanagawa
发明人： Kenji Ichikawa , Osamu Nomura , Akihiro Morita , Yoichiro Kawabe , Hideaki Fujiwara , Koyo Yanagawa
IPC分类号： B22D11/111
CPC分类号： B22D11/111
摘要： A mold additive suitable for use in a mold for continuous casting of steel which comprises, as its base material, at least 50% by weight of synthetic calcium silicate which contains CaO and SiO.sub.2 in a total amount not less than 70% by weight, and whose CaO/SiO.sub.2 ratio is not lower than 1.20. A mold additive of low bulk density and superior in heat insulation can be obtained and its CaO/SiO.sub.2 ratio can be widely adjusted.
摘要翻译：一种适合用于连续铸造钢的模具的模具添加剂，其包含至少50重量％的合成硅酸钙作为其基材，所述合成硅酸钙含有不少于70重量％的CaO和SiO 2，以及其CaO / SiO2比不低于1.20。可以获得低堆积密度和绝热性优良的模具添加剂，可以广泛调整其CaO / SiO2比例。

8. 发明授权

US07564106B2 Semiconductor device comprising gate electrode 有权
标题翻译：包括栅电极的半导体器件
公开(公告)号：US07564106B2
公开(公告)日：2009-07-21
申请号：US11711726
申请日：2007-02-28
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01L29/78
CPC分类号： H01L21/28079 , H01L21/28035 , H01L21/823842 , H01L21/823857 , H01L21/823864
摘要： A semiconductor device capable of reducing a threshold voltage is obtained. The semiconductor device includes a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween, and a gate electrode formed on the channel region through a gate insulating film and including a metal-containing layer arranged in the vicinity of an interface between the gate insulating film and the gate electrode, wherein the metal-containing layer is so formed in the form of dots as to partially cover the surface of the gate insulating film, and the average distance between dots forming the metal-containing layer is set to not more than a diameter of the dot of the metal-containing layer.
摘要翻译：获得能够降低阈值电压的半导体器件。半导体器件包括形成在半导体区域的主表面上以保持其间的沟道区的一对源极/漏极区，以及通过栅极绝缘膜形成在沟道区上的栅极，并且包括含有金属的层栅极绝缘膜和栅电极之间的界面附近，其中含金属层以点的形式形成为部分地覆盖栅极绝缘膜的表面，并且形成金属的点之间的平均距离含有层被设定为不大于含金属层的点的直径。

9. 发明申请

US20060267095A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060267095A1
公开(公告)日：2006-11-30
申请号：US11443152
申请日：2006-05-31
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01L27/12
CPC分类号： H01L21/823842
摘要： A semiconductor device capable of reducing deterioration of electron mobility while suppressing depletion of gate electrodes is provided. This semiconductor device includes a metal-containing layer so formed that at least either a first gate electrode or a second gate electrode partially covers a corresponding first or second gate insulating film and a semiconductor layer formed on the metal-containing layer to come into contact with a portion of the corresponding first or second gate insulating film not covered with the metal-containing layer. The first and second gate electrodes contain metals different from each other.
摘要翻译：提供能够减少电子迁移率劣化并抑制栅电极耗尽的半导体器件。该半导体装置包括如此形成的含金属层，使得第一栅极电极或第二栅电极中的至少一个部分地覆盖相应的第一或第二栅极绝缘膜和形成在含金属层上的半导体层以与相应的第一或第二栅绝缘膜的一部分未被含金属层覆盖。第一和第二栅电极包含彼此不同的金属。

10. 发明申请

US20050260818A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050260818A1
公开(公告)日：2005-11-24
申请号：US11132197
申请日：2005-05-19
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： H01L29/41 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/66621 , H01L29/4908 , H01L29/66553 , H01L29/66772 , H01L29/78621 , H01L29/78636
摘要： A method for fabricating a semiconductor device includes:isolating a SOI layer on a buried oxide film with a pair of element isolation regions having a perpendicular sidewall; depositing a poly-crystal silicon layer on the isolated SOI layer; implanting a dopant into the poly-crystal silicon layer; depositing a silicon oxide film on the poly-crystal silicon layer; forming a recessed portion by selectively removing the silicon oxide film and the poly-crystal silicon layer in a gate bearing region and then selectively removing the SOI layer in the gate bearing region to a predetermined depth; forming a sidewall spacer on the side wall of the recessed portion; forming source and drain regions by allowing a dopant to diffuse from the poly-crystal silicon layer into the SOI layer; and forming a gate electrode by depositing a gate metal layer after a gate insulating film is formed on the bottom of the recessed portion.
摘要翻译：一种用于制造半导体器件的方法，包括：利用具有垂直侧壁的一对元件隔离区域在掩埋氧化膜上隔离SOI层; 在隔离的SOI层上沉积多晶硅层; 将掺杂剂注入到所述多晶硅层中; 在所述多晶硅层上沉积氧化硅膜; 通过选择性地去除栅极承载区域中的氧化硅膜和多晶硅层，然后选择性地将栅极承载区域中的SOI层去除到预定深度来形成凹陷部分; 在所述凹部的侧壁上形成侧壁间隔物; 通过使掺杂剂从多晶硅层扩散到SOI层中形成源区和漏区; 以及在凹陷部分的底部上形成栅极绝缘膜之后，通过沉积栅极金属层来形成栅电极。

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