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1. 发明授权

US4914043A Method of making an integrated light-triggered and light-quenched static induction thyristor 失效
标题翻译：制造集成光触发和光淬火静电感应晶闸管的方法
公开(公告)号：US4914043A
公开(公告)日：1990-04-03
申请号：US338271
申请日：1989-04-14
申请人： Jun-ichi Nishizawa , Takashige Tamamushi , Ken-ichi Nonaka
发明人： Jun-ichi Nishizawa , Takashige Tamamushi , Ken-ichi Nonaka
IPC分类号： H01L29/74 , H01L21/332 , H01L27/144 , H01L29/08 , H01L29/739 , H01L29/744 , H01L31/111 , H03K17/78
CPC分类号： H01L31/1116 , H01L27/1443 , H01L29/0834 , H01L29/7392
摘要： An integrated light-triggered and light-quenched static induction thyristor and fabrication process thereof adapted in such a manner that an integrated SIPT operates in the normal mode in order to enhance current gain, tail current generated at the light-quenching time is reduced in order to enhance turn-off gain, and an buried-gate type of light-triggered static induction thyristor and a photo-darlington circuit composed of a first and second static induction phototransistors are integrated on a high-resistivity substrate in order to permit manufacturing said thyristor compact as a whole in facilitated processes.

2. 发明授权

US4866500A Integrated light-triggered and light-quenched static induction thyristor and making method thereof 失效
标题翻译：集成光触发和光淬火静态感应晶闸管及其制作方法
公开(公告)号：US4866500A
公开(公告)日：1989-09-12
申请号：US100368
申请日：1987-09-23
申请人： Jun-ichi Nishizawa , Takashige Tamamushi , Ken-ichi Nonaka
发明人： Jun-ichi Nishizawa , Takashige Tamamushi , Ken-ichi Nonaka
IPC分类号： H01L29/74 , H01L21/332 , H01L27/144 , H01L29/08 , H01L29/739 , H01L29/744 , H01L31/111 , H03K17/78
CPC分类号： H01L31/1116 , H01L27/1443 , H01L29/0834 , H01L29/7392
摘要： An integrated light-triggered and light-quenched static induction thyristor and fabrication process thereof adapted in such a manner that an integrated SIPT operates in the normal mode in order to enhance current gain, tail current generated at the light-quenching time is reduced in order to enhance turn-off gain, and a buried-gate type of light-triggered static induction thyristor and a photo-darlington circuit composed of a first and second static induction phototransistors are integrated on a high-resistivity substrate in order to permit manufacturing said thyristor compact as a whole in facilitated processes.
摘要翻译：一种集成的光触发和轻型静态感应晶闸管及其制造方法，其以集成SIPT在正常模式下操作以增强电流增益的方式进行调节，从而按照顺序减少在光猝灭时间产生的尾流电流以提高关断增益，并且在高电阻率基板上集成了由第一和第二静电感应光电晶体管组成的掩埋栅型光触发静电感应晶闸管和光达林顿电路，以便制造所述晶闸管紧凑的整体在便利的过程中。

3. 发明授权

US5017991A Light quenchable thyristor device 失效
标题翻译：光淬火晶闸管器件
公开(公告)号：US5017991A
公开(公告)日：1991-05-21
申请号：US259438
申请日：1988-10-14
申请人： Jun-ichi Nishizawa , Takashige Tamamushi , Ken-ichi Nonaka
发明人： Jun-ichi Nishizawa , Takashige Tamamushi , Ken-ichi Nonaka
IPC分类号： H01L29/10 , H01L29/739 , H01L29/74 , H01L29/744 , H01L31/10 , H01L31/111 , H02M1/08 , H03K17/78 , H03K17/79
CPC分类号： H01L29/102 , H01L29/1016 , H01L29/1066 , H01L29/7392 , H01L29/744 , H01L31/1113 , H03K17/79
摘要： A thyristor device comprising an SI (Static induction) thyristor or beam base thyristor and an SIT (static induction transistor) or SIT-mode bipolar transistor connected to the gate of the thyristor in order to make it possible to turn-on and-off a direct current and voltage at a high speed with a light. In the thyristor part, the SIT gate structure or SIT-mode beam base structure exists in the first gate or base region or second gate or base region so that, at the time of the triggering operation, a very high switching efficiency will be obtained.
摘要翻译：一种晶闸管器件，其包括连接到晶闸管的栅极的SI（静态感应）晶闸管或光束基极晶闸管和SIT（静态感应晶体管）或SIT模式双极晶体管，以便使得能够导通和断开直流电和电压高速带光。在晶闸管部分中，在第一栅极或基极区域或第二栅极或基极区域中存在SIT栅极结构或SIT模式波束基极结构，使得在触发操作时将获得非常高的开关效率。

4. 发明申请

US20110222257A1 INVERTER UNIT, INTEGRATED CIRCUIT CHIP, AND VEHICLE DRIVE APPARATUS 有权
标题翻译：逆变器单元，集成电路芯片和车辆驱动装置
公开(公告)号：US20110222257A1
公开(公告)日：2011-09-15
申请号：US13111122
申请日：2011-05-19
申请人： Hitoshi SUMIDA , Akinobu Teramoto , Ken-ichi Nonaka , Toshio Naka
发明人： Hitoshi SUMIDA , Akinobu Teramoto , Ken-ichi Nonaka , Toshio Naka
IPC分类号： H05K7/06
CPC分类号： H02P27/06 , B60L3/003 , B60L2210/20 , H02M7/003 , Y02T10/725
摘要： A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.
摘要翻译：一个小型化，低成本的高可靠性逆变器单元。控制电路部分，用于控制包括在逆变器电路部分中的高击穿电压半导体元件的操作定时;以及第一和第二驱动和异常检测电路部分，用于根据操作时间输出用于驱动高击穿电压半导体元件的驱动信号，将逆变器电路部分的异常返回到控制电路部分形成在作为一个集成电路芯片的SOI衬底上。在集成电路芯片上，参考电位不同的电路形成区域通过电介质彼此分离。形成用于传输由电介质分离的电路形成区域之间交换的信号的多个电平移位器。

5. 发明申请

US20070032002A1 Ion implantation mask and method for manufacturing same, silicon carbide semiconductor device using ion implantation mask, and method for manufacturing same 失效
标题翻译：离子注入掩模及其制造方法，使用离子注入掩模的碳化硅半导体器件及其制造方法
公开(公告)号：US20070032002A1
公开(公告)日：2007-02-08
申请号：US11496627
申请日：2006-08-01
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
IPC分类号： H01L21/337 , H01L21/425 , H01L21/265 , H01L21/336 , H01L21/00
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/66068 , Y10S438/931
摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.
摘要翻译：公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。所获得的离子注入掩模用于形成更深的选择性导电区域。

6. 发明授权

US08460994B2 Bipolar semiconductor device and manufacturing method thereof 有权
标题翻译：双极半导体器件及其制造方法
公开(公告)号：US08460994B2
公开(公告)日：2013-06-11
申请号：US11919350
申请日：2006-06-09
申请人： Ken-ichi Nonaka
发明人： Ken-ichi Nonaka
IPC分类号： H01L21/331
CPC分类号： H01L29/73 , H01L29/0607 , H01L29/0804 , H01L29/1608 , H01L29/66068 , H01L29/732
摘要： A semiconductor crystal includes a recombination-inhibiting semiconductor layer (17) of a second conductive type that is disposed in the vicinity of the surface between a base contact region (16) and emitter regions (14) and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.
摘要翻译：半导体晶体包括：第二导电类型的复合抑制半导体层（17），其设置在基极接触区域（16）和发射极区域（14）之间的表面附近，并且将半导体表面分离从主要传导正空穴电流的部分和电子电流的表面状态的数量。可以抑制重组，从而提高电流放大系数，降低ON电压。

7. 发明授权

US08105927B2 Method for manufacturing ion implantation mask, and method for manufacturing silicon carbide semiconductor device 有权
标题翻译：用于制造离子注入掩模的方法，以及制造碳化硅半导体器件的方法
公开(公告)号：US08105927B2
公开(公告)日：2012-01-31
申请号：US12716916
申请日：2010-03-03
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
IPC分类号： H01L21/425
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/66068 , Y10S438/931
摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.
摘要翻译：公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。所获得的离子注入掩模用于形成更深的选择性导电区域。

8. 发明申请

US20100001290A1 BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：双极半导体器件及其制造方法
公开(公告)号：US20100001290A1
公开(公告)日：2010-01-07
申请号：US11919350
申请日：2006-06-09
申请人： Ken-ichi Nonaka
发明人： Ken-ichi Nonaka
IPC分类号： H01L29/73 , H01L29/24 , H01L21/331
CPC分类号： H01L29/73 , H01L29/0607 , H01L29/0804 , H01L29/1608 , H01L29/66068 , H01L29/732
摘要： A semiconductor crystal includes a recombination-inhibiting semiconductor layer (17) of a second conductive type that is disposed in the vicinity of the surface between a base contact region (16) and emitter regions (14) and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.
摘要翻译：半导体晶体包括：第二导电类型的复合抑制半导体层（17），其设置在基极接触区域（16）和发射极区域（14）之间的表面附近，并且将半导体表面分离从主要传导正空穴电流的部分和电子电流的表面状态的数量。可以抑制重组，从而提高电流放大系数，降低ON电压。

9. 发明授权

US07867836B2 Method for manufacturing junction semiconductor device 失效
标题翻译：结半导体器件的制造方法
公开(公告)号：US07867836B2
公开(公告)日：2011-01-11
申请号：US12203660
申请日：2008-09-03
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译：一种用于制造具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区域的结半导体器件的方法，包括形成在另一个上的第一导电类型的低电阻层的源极区域半导体晶体的表面，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及复合抑制半导体层设置在栅极区域和源极区域之间的半导体晶体的表面附近的第二导电类型。

10. 发明授权

US07449734B2 Junction semiconductor device and method for manufacturing the same 失效
标题翻译：结半导体器件及其制造方法
公开(公告)号：US07449734B2
公开(公告)日：2008-11-11
申请号：US11386850
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译：具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区的结半导体器件，包括形成在半导体的另一个表面上的第一导电类型的低电阻层的源极区域晶体，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及第二导电类型的复合抑制半导体层设置在栅极区域和源极区域之间的半导体晶体的表面附近。

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