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1. 发明授权

US08221045B2 Semiconductor device manufacturing apparatus and wafer loading/unloading method thereof 有权
标题翻译：半导体器件制造装置及其晶片装载/卸载方法
公开(公告)号：US08221045B2
公开(公告)日：2012-07-17
申请号：US12350705
申请日：2009-01-08
申请人： Jun-Sig Park , Jung-Hyeon Kim , Jin-Ho Shin , Gennady Ivanov
发明人： Jun-Sig Park , Jung-Hyeon Kim , Jin-Ho Shin , Gennady Ivanov
IPC分类号： H01L21/677
CPC分类号： C23C16/4583 , H01L21/67109 , H01L21/67383 , Y10S414/136 , Y10S414/141
摘要： A semiconductor manufacturing apparatus and a wafer loading/unloading method thereof increase productivity. The semiconductor manufacturing apparatus includes a first boat and a second boat having a plurality of first slots and a plurality of second slots, respectively, and disposed such that the first slots and the second slots alternate each other, the first boat mounting a plurality of first wafers in the first slots to direct front faces of the first wafers in a predetermined direction, the second boat mounting a plurality of second wafers in the second slots to direct back faces of the second wafers in the predetermined direction; a reaction tube having an opening and containing the first and second boats mounting the first and second wafers; a plate sealing up the opening of the reaction tube containing the first boat and the second boat; a reaction gas supplier supplying reaction gas into the sealed reaction tube for a predetermined process; and a reaction gas exhauster exhausting the reaction gas from the reaction tube to the external of the reaction tube after the predetermined process.
摘要翻译：半导体制造装置及其晶片装载/卸载方法提高了生产率。半导体制造装置包括分别具有多个第一槽和多个第二槽的第一船和第二船，并且被布置成使得第一槽和第二槽彼此交替，第一船安装多个第一槽在第一槽中的晶片以预定方向引导第一晶片的前表面，第二船在第二槽中安装多个第二晶片，以沿预定方向引导第二晶片的后表面; 反应管，其具有开口并且容纳安装所述第一和第二晶片的所述第一和第二船; 密封包含第一船和第二船的反应管的开口的板; 将反应气体供给到密封反应管中以进行预定处理的反应气体供给装置; 以及反应气体排出器，其在预定处理之后将反应气体从反应管排出到反应管的外部。

2. 发明申请

US20090191042A1 SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND WAFER LOADING/UNLOADING METHOD THEREOF 有权
标题翻译：半导体器件制造装置及其加载/卸载方法
公开(公告)号：US20090191042A1
公开(公告)日：2009-07-30
申请号：US12350705
申请日：2009-01-08
申请人： Jun-Sig Park , Jung-Hyeon Kim , Jin-Ho Shin , Gennady Ivanov
发明人： Jun-Sig Park , Jung-Hyeon Kim , Jin-Ho Shin , Gennady Ivanov
IPC分类号： H01L21/677 , C23C16/458 , H01L21/30
CPC分类号： C23C16/4583 , H01L21/67109 , H01L21/67383 , Y10S414/136 , Y10S414/141
摘要： A semiconductor manufacturing apparatus and a wafer loading/unloading method thereof increase productivity. The semiconductor manufacturing apparatus includes a first boat and a second boat having a plurality of first slots and a plurality of second slots, respectively, and disposed such that the first slots and the second slots alternate each other, the first boat mounting a plurality of first wafers in the first slots to direct front faces of the first wafers in a predetermined direction, the second boat mounting a plurality of second wafers in the second slots to direct back faces of the second wafers in the predetermined direction; a reaction tube having an opening and containing the first and second boats mounting the first and second wafers; a plate sealing up the opening of the reaction tube containing the first boat and the second boat; a reaction gas supplier supplying reaction gas into the sealed reaction tube for a predetermined process; and a reaction gas exhauster exhausting the reaction gas from the reaction tube to the external of the reaction tube after the predetermined process.
摘要翻译：半导体制造装置及其晶片装载/卸载方法提高了生产率。半导体制造装置包括分别具有多个第一槽和多个第二槽的第一船和第二船，并且被布置成使得第一槽和第二槽彼此交替，第一船安装多个第一槽在所述第一槽中的晶片在预定方向上引导所述第一晶片的前表面，所述第二船在所述第二槽中安装多个第二晶片以沿所述预定方向引导所述第二晶片的背面; 反应管，其具有开口并且容纳安装所述第一和第二晶片的所述第一和第二船; 密封包含第一船和第二船的反应管的开口的板; 将反应气体供给到密封反应管中以进行预定处理的反应气体供给装置; 以及反应气体排出器，其在预定处理之后将反应气体从反应管排出到反应管的外部。

3. 发明授权

US08547766B2 Area-efficient data line layouts to suppress the degradation of electrical characteristics 有权
标题翻译：区域高效的数据线布局，以抑制电气特性的恶化
公开(公告)号：US08547766B2
公开(公告)日：2013-10-01
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

4. 发明授权

US08187914B2 Methods of forming a phase change memory device 有权
标题翻译：形成相变存储器件的方法
公开(公告)号：US08187914B2
公开(公告)日：2012-05-29
申请号：US12731637
申请日：2010-03-25
申请人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
发明人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
IPC分类号： H01L21/20
CPC分类号： H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.
摘要翻译：提供形成相变存储器件的方法。可以制备具有下电极和层间绝缘层的半导体器件。下电极可以被层间绝缘层包围。可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。源气体可以同时注入到处理室中。相变材料层可以通过层间绝缘层与下电极接触。可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。可以在相变存储单元上形成上电极。

5. 发明授权

US08130577B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08130577B2
公开(公告)日：2012-03-06
申请号：US12590417
申请日：2009-11-06
申请人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C5/025 , G11C7/1012 , G11C7/12 , G11C2207/002
摘要： A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.
摘要翻译：半导体存储器件包括具有存储单元的子存储单元阵列区域，每个存储单元分别连接在沿第一方向延伸的字线和沿着与字线的第一延伸方向正交的第二方向延伸的位线和一个子字线驱动器区域，设置在副存储单元阵列区域的第一方向的一侧，并且包括激活字线的子字线驱动器。感测区域设置在副存储单元阵列区域的第二方向的一侧，并且包括响应于通过驱动信号线传送的信号而对位线进行预充电的均衡器，以及至少一个第一控制信号驱动器，其激活响应于通过控制信号线传送的信号的反相控制信号线。配置在副字线驱动器区域和感测区域之间的交叉点处的连接区域，其中反相控制信号线连接到驱动信号线。

6. 发明授权

US07906423B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07906423B2
公开(公告)日：2011-03-15
申请号：US12650093
申请日：2009-12-30
申请人： Hyo-Jae Bang , Heui-Seog Kim , Dong-Chun Lee , Seong-Chan Han , Jung-Hyeon Kim
发明人： Hyo-Jae Bang , Heui-Seog Kim , Dong-Chun Lee , Seong-Chan Han , Jung-Hyeon Kim
IPC分类号： H01L21/44
CPC分类号： H05K3/303 , H05K2201/0305 , H05K2201/09781 , H05K2201/10689 , H05K2201/2036 , Y02P70/613
摘要： A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.
摘要翻译：半导体器件包括半导体封装，电路板和间隔保持元件。半导体封装具有从主体突出的主体和引线。电路板具有与引线电连接的第一焊盘。间隔保持构件插入在电路板和主体之间。间隔保持构件保持引线与第一焊盘之间的间隔。因此，均匀地保持引线和焊盘之间的间隔，从而提高了半导体器件的热和/或机械可靠性。

7. 发明授权

US07841505B2 Wire clamp and wire bonding apparatus having the same 有权
标题翻译：具有相同的线夹和引线接合装置
公开(公告)号：US07841505B2
公开(公告)日：2010-11-30
申请号：US12320964
申请日：2009-02-10
申请人： Sung-Soo Lee , Ki-Taik Oh , Jung-Hyeon Kim
发明人： Sung-Soo Lee , Ki-Taik Oh , Jung-Hyeon Kim
IPC分类号： B23K37/00
CPC分类号： H01L24/85 , B23K20/007 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/45144 , H01L2224/48227 , H01L2224/48463 , H01L2224/78301 , H01L2224/786 , H01L2224/851 , H01L2224/85205 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A wire clamp includes a pair of clamp arms at a predetermined distance from each other to define an interval therebetween for a bonding wire, a clamp body coupled to the clamp arms, the clamp body configured to adjust the predetermined distance between the clamp arms with respect to a process to be performed, a clamping section in each clamp arm, the clamping section having concave portions facing the interval between the clamp arms, the concave portions being configured to contact the bonding wire when the clamp arms are brought close together, and at least one abrasion prevention member in each clamping section, the abrasion prevention members being configured to prevent abrasion during contact with the bonding wire.
摘要翻译：电线夹具包括彼此隔开预定距离的一对夹持臂，以在其间限定用于接合线的间隔，联接到夹紧臂的夹具本体，夹具主体被配置为相对于夹具臂之间的预定距离调整对于要执行的处理，每个夹持臂中的夹持部分，夹持部分具有面对夹紧臂之间的间隔的凹部，凹部被构造成在夹紧臂靠近在一起时与接合线接触，并且在每个夹紧部分中的至少一个防磨损构件，所述防磨构件被构造成防止在与所述接合线接触期间的磨损。

8. 发明申请

US20090271982A1 Method of forming a wiring having carbon nanotube 有权
标题翻译：形成具有碳纳米管的布线的方法
公开(公告)号：US20090271982A1
公开(公告)日：2009-11-05
申请号：US12387299
申请日：2009-04-29
申请人： Sun-Woo Lee , Seong-Ho Moon , Dong-Woo Kim , Jung-Hyeon Kim , Hong-Sik Yoon
发明人： Sun-Woo Lee , Seong-Ho Moon , Dong-Woo Kim , Jung-Hyeon Kim , Hong-Sik Yoon
IPC分类号： H05K3/10
CPC分类号： H01L21/76879 , H01L21/76849 , H01L23/5252 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10T29/49117 , Y10T29/4913 , Y10T29/49155 , H01L2924/00
摘要： In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained.
摘要翻译：在形成具有碳纳米管的布线的方法中，在基板上形成下布线，并且在下布线上形成催化剂层。在衬底上形成绝缘中间层以覆盖催化剂层，并且通过绝缘中间层形成开口以暴露催化剂层的上表面。在开口部形成有碳纳米管布线，在碳纳米管布线和绝缘中间层上形成上部配线，与碳纳米管配线电连接。在碳纳米管布线和上布线之间产生热应力，以产生形成在碳纳米管布线表面上的天然氧化物层的电介质击穿。可以获得碳纳米管布线和上布线之间的电阻降低的布线。

9. 发明申请

US20090245079A1 OPTICAL RECORDING MEDIUM HAVING SUPER-RESOLUTION STRUCTURE FOR IMPROVEMENT OF REPRODUCING STABILITY AND NOISE CHARACTERISTIC IN LOW FREQUENCY BAND 有权
标题翻译：具有超分辨率结构的光学记录介质，用于改善低频重现稳定性和噪声特性
公开(公告)号：US20090245079A1
公开(公告)日：2009-10-01
申请号：US12260509
申请日：2008-10-29
申请人： Wook Yeon Hwang , Jooho Kim , Jung-Hyeon Kim , Taek Sung Lee , Byung Ki Cheong , Hyun Seok Lee , Suyoun Lee , Won Mok Kim , Jeung-hyun Jeong
发明人： Wook Yeon Hwang , Jooho Kim , Jung-Hyeon Kim , Taek Sung Lee , Byung Ki Cheong , Hyun Seok Lee , Suyoun Lee , Won Mok Kim , Jeung-hyun Jeong
IPC分类号： G11B7/24
CPC分类号： G11B7/252 , G11B7/24065 , G11B7/2531 , G11B7/2533 , G11B7/259 , G11B7/266 , G11B2007/24304 , G11B2007/24306 , G11B2007/2432
摘要： A super-resolution optical recording medium includes a reflective layer formed on a substrate, a recording layer for recording information thereon, a super-resolution layer made of a chalcogenide semiconductor material, and a first and a second dielectric layers laminated on upper and lower surfaces of the super-resolution layer. The recording layer is made of a material that has a decomposition temperature higher than an information reproduction temperature and does not form bubble recording marks during recording, and the super-resolution layer contains one or more elements selected from the group consisting of nitrogen, oxygen, carbon, and boron.
摘要翻译：超分辨率光记录介质包括形成在基板上的反射层，用于在其上记录信息的记录层，由硫族化物半导体材料制成的超分辨率层，以及层叠在上表面和下表面上的第一和第二介电层的超分辨率层。记录层由分解温度高于信息再现温度的材料制成，并且在记录期间不形成气泡记录标记，并且超分辨率层含有一种或多种选自氮，氧，碳和硼。

10. 发明申请

US20090200362A1 METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：制造半导体封装的方法
公开(公告)号：US20090200362A1
公开(公告)日：2009-08-13
申请号：US12369257
申请日：2009-02-11
申请人： Ky-Hyun JUNG , Jae-Yong Park , Heui-Seog Kim , Wha-Su Sin , Jung-Hyeon Kim
发明人： Ky-Hyun JUNG , Jae-Yong Park , Heui-Seog Kim , Wha-Su Sin , Jung-Hyeon Kim
IPC分类号： B23K31/02 , B23K1/20
CPC分类号： B23K1/0016 , B23K1/0053 , B23K1/008 , B23K1/206 , B23K2101/42 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L25/105 , H01L2224/05568 , H01L2224/05573 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01077 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19043 , H01L2924/3651 , H05K3/3436 , H05K3/3463 , H05K2201/10734 , H01L2224/05599
摘要： In a lead-free solder, a semiconductor package and a method of manufacturing the semiconductor package, the lead-free solder includes about 3.5 percent by weight to about 6 percent by weight of silver, about 0.05 percent by weight to about 0.5 percent by weight of copper and a remainder of tin. The lead-free solder is employed in the semiconductor package. The lead-free solder has high impact resistance and high heat resistance to reduce failures of the semiconductor package.
摘要翻译：在无铅焊料，半导体封装和半导体封装的制造方法中，无铅焊料包括约3.5重量％至约6重量％的银，约0.05重量％至约0.5重量％的铜和余下的锡。在半导体封装中采用无铅焊料。无铅焊料具有高抗冲击性和高耐热性，以减少半导体封装的故障。

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