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1. 发明授权

US08547766B2 Area-efficient data line layouts to suppress the degradation of electrical characteristics 有权
标题翻译：区域高效的数据线布局，以抑制电气特性的恶化
公开(公告)号：US08547766B2
公开(公告)日：2013-10-01
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

2. 发明授权

US08130577B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08130577B2
公开(公告)日：2012-03-06
申请号：US12590417
申请日：2009-11-06
申请人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C5/025 , G11C7/1012 , G11C7/12 , G11C2207/002
摘要： A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.
摘要翻译：半导体存储器件包括具有存储单元的子存储单元阵列区域，每个存储单元分别连接在沿第一方向延伸的字线和沿着与字线的第一延伸方向正交的第二方向延伸的位线和一个子字线驱动器区域，设置在副存储单元阵列区域的第一方向的一侧，并且包括激活字线的子字线驱动器。感测区域设置在副存储单元阵列区域的第二方向的一侧，并且包括响应于通过驱动信号线传送的信号而对位线进行预充电的均衡器，以及至少一个第一控制信号驱动器，其激活响应于通过控制信号线传送的信号的反相控制信号线。配置在副字线驱动器区域和感测区域之间的交叉点处的连接区域，其中反相控制信号线连接到驱动信号线。

3. 发明申请

US20100118615A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20100118615A1
公开(公告)日：2010-05-13
申请号：US12590417
申请日：2009-11-06
申请人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C7/12 , G11C7/10
CPC分类号： G11C7/08 , G11C5/025 , G11C7/1012 , G11C7/12 , G11C2207/002
摘要： A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.
摘要翻译：半导体存储器件包括具有存储单元的子存储单元阵列区域，每个存储单元分别连接在沿第一方向延伸的字线和沿着与字线的第一延伸方向正交的第二方向延伸的位线和一个子字线驱动器区域，设置在副存储单元阵列区域的第一方向的一侧，并且包括激活字线的子字线驱动器。感测区域设置在副存储单元阵列区域的第二方向的一侧，并且包括响应于通过驱动信号线传送的信号而对位线进行预充电的均衡器，以及至少一个第一控制信号驱动器，其激活响应于通过控制信号线传送的信号的反相控制信号线。配置在副字线驱动器区域和感测区域之间的交叉点处的连接区域，其中反相控制信号线连接到驱动信号线。

4. 发明申请

US20100259963A1 Data line layouts 有权
标题翻译：数据线布局
公开(公告)号：US20100259963A1
公开(公告)日：2010-10-14
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

5. 发明申请

US20080164894A1 System and method for testing semiconductor integrated circuit in parallel 审中-公开
标题翻译：半导体集成电路并行测试的系统和方法
公开(公告)号：US20080164894A1
公开(公告)日：2008-07-10
申请号：US12006560
申请日：2008-01-03
申请人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
发明人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
IPC分类号： G01R31/26
CPC分类号： G01R31/2886 , G01R31/2889
摘要： A system and method for testing a semiconductor integrated circuit (IC) in parallel includes a probe chuck, a test head, and a test controller. The probe chuck loads a plurality of different types of semiconductor DUTs. The test head provides a plurality of circuit sites to independently and simultaneously test the different types of semiconductor DUTs, and the test controller controls the test head and the probe chuck.
摘要翻译：用于同时测试半导体集成电路（IC）的系统和方法包括探针卡盘，测试头和测试控制器。探头卡盘装载多种不同类型的半导体DUT。测试头提供多个电路位置，以独立并同时测试不同类型的半导体DUT，并且测试控制器控制测试头和探头卡盘。

6. 发明申请

US20080164898A1 Probe card for test of semiconductor chips and method for test of semiconductor chips using the same 审中-公开
标题翻译：用于半导体芯片测试的探针卡和使用其的半导体芯片的测试方法
公开(公告)号：US20080164898A1
公开(公告)日：2008-07-10
申请号：US12005888
申请日：2007-12-28
申请人： Sung-Hoon Bae , Jung-Hyeon Kim , Young-Soo An , Ho-Jeong Choi , Myoung-Sub Kim
发明人： Sung-Hoon Bae , Jung-Hyeon Kim , Young-Soo An , Ho-Jeong Choi , Myoung-Sub Kim
IPC分类号： G01R31/02
CPC分类号： G01R1/07385 , G01R1/07342
摘要： There are provided a probe card for test of semiconductor chips and a method for testing semiconductor chips using the probe card. In implementing the probe card for electrically testing semiconductor chips, the probe blocks corresponding to multiple selected ones of the semiconductor chips on the wafer can be selected so that the selected semiconductor chips are EDS tested in a one-step process. As the selected semiconductor chips are EDS tested in a one-step process, equipment efficiency is improved, and statistical objectivity of data indicating characteristics of the wafer can be achieved.
摘要翻译：提供了用于半导体芯片测试的探针卡和使用探针卡测试半导体芯片的方法。在实现用于电测试半导体芯片的探针卡时，可以选择对应于晶片上的多个选定的半导体芯片的探针块，使得所选择的半导体芯片在一步法中进行EDS测试。由于所选择的半导体芯片在一步法中进行了EDS测试，所以提高了设备效率，并且可以实现表示晶片特性的数据的统计客观性。

7. 发明申请

US20080164901A1 Multilayer type test board assembly for high-precision inspection 有权
标题翻译：多层型测试板组件进行高精度检测
公开(公告)号：US20080164901A1
公开(公告)日：2008-07-10
申请号：US12006543
申请日：2008-01-03
申请人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
发明人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
IPC分类号： G01R1/02
CPC分类号： G01R31/2851 , G01R1/04 , H05K1/144 , H05K1/148 , H05K2201/042 , H05K2201/09972 , H05K2201/10371
摘要： There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.
摘要翻译：提供了一种用于高精度检测的多层型测试板组件。多层测试板组件包括：根据功能彼此分离的多个测试板，具有输入/输出信号端子，并且包括至少一个测试板，每个测试板具有第一部分，其中第一安装器件对电气的影响敏感信号被安装，并且第二部分安装对电信号的影响不敏感的第二安装装置; 间隔件通过以预定的间隔隔开测试板来平行布置测试板; 连接电缆连接到测试板的输入/输出信号端子; 以及形成在所述至少一个测试板中的每一个上的信号屏蔽栅栏，以便保护所述第一安装装置免受由所述第二安装装置产生的电信号。

8. 发明授权

US07786721B2 Multilayer type test board assembly for high-precision inspection 有权
标题翻译：多层型测试板组件进行高精度检测
公开(公告)号：US07786721B2
公开(公告)日：2010-08-31
申请号：US12006543
申请日：2008-01-03
申请人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
发明人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2851 , G01R1/04 , H05K1/144 , H05K1/148 , H05K2201/042 , H05K2201/09972 , H05K2201/10371
摘要： There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.
摘要翻译：提供了一种用于高精度检测的多层型测试板组件。多层测试板组件包括：根据功能彼此分离的多个测试板，具有输入/输出信号端子，并且包括至少一个测试板，每个测试板具有第一部分，其中第一安装装置对电气的影响敏感信号被安装，并且第二部分安装对电信号的影响不敏感的第二安装装置; 间隔件通过以预定的间隔隔开测试板来平行布置测试板; 连接电缆连接到测试板的输入/输出信号端子; 以及形成在所述至少一个测试板中的每一个上的信号屏蔽栅栏，以便保护所述第一安装装置免受由所述第二安装装置产生的电信号。

9. 发明授权

US08139949B2 Electrical signal transmission module, method of transmitting electric signals and electrical inspection apparatus having the same 有权
标题翻译：电信号传输模块，发送电信号的方法和具有该信号的电气检查装置
公开(公告)号：US08139949B2
公开(公告)日：2012-03-20
申请号：US12179015
申请日：2008-07-24
申请人： Sang-Hoon Lee , Ho-Jeong Choi , Se-Jang Oh , Young-Soo An , Gyu-Yeol Kim
发明人： Sang-Hoon Lee , Ho-Jeong Choi , Se-Jang Oh , Young-Soo An , Gyu-Yeol Kim
IPC分类号： H04B10/12
CPC分类号： H04B10/2504 , G01R31/2889 , H04B10/801
摘要： An electrical signal transmission module includes a plurality of optical signal lines and a plurality of electrical signal lines. The plurality of optical signal lines converting a first externally input electrical signal into an optical signal, transmitting the optical signal, converting the optical signal back into the first electrical signal, and outputting the first electrical signal. The plurality of electrical signal lines transmitting a second externally input electrical signal and outputting the second electrical signal.
摘要翻译：电信号传输模块包括多个光信号线和多个电信号线。多个光信号线将第一外部输入的电信号转换为光信号，发送光信号，将光信号转换回第一电信号，并输出第一电信号。多个电信号线发送第二外部输入电信号并输出第二电信号。

10. 发明授权

US07538566B2 Electrical test system including coaxial cables 有权
标题翻译：电测试系统包括同轴电缆
公开(公告)号：US07538566B2
公开(公告)日：2009-05-26
申请号：US11926172
申请日：2007-10-29
申请人： Young-Soo An , Se-Jang Oh , Jung-Hyun Nam
发明人： Young-Soo An , Se-Jang Oh , Jung-Hyun Nam
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2889
摘要： An electrical test system includes a test head, a performance board, a probe card and coaxial cables. The performance board includes a first side and an opposite second side, where the first side of the performance board is electrically connected to the test head and the second side of the performance board includes first coaxial cable connection portions. The probe card includes a first side and an opposite second side, where the first side of the probe card includes second coaxial cable connection portions and the second side includes a wafer test probes. The coaxial cables respectively electrically connect the first coaxial cable connection portions of the performance board to the second coaxial cable connection portions of the probe card.
摘要翻译：电气测试系统包括测试头，演奏板，探针卡和同轴电缆。所述性能板包括第一侧和相对的第二侧，其中所述性能板的第一侧电连接到所述测试头，并且所述性能板的第二侧包括第一同轴电缆连接部分。探针卡包括第一侧和相对的第二侧，其中探针卡的第一侧包括第二同轴电缆连接部分，并且第二侧包括晶片测试探针。同轴电缆分别将性能板的第一同轴电缆连接部分电连接到探针卡的第二同轴电缆连接部分。

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