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1. 发明授权

US09401428B2 Semiconductor devices including gate pattern, multi-channel active pattern and diffusion layer 有权
标题翻译：半导体器件包括栅极图案，多通道有源图案和扩散层
公开(公告)号：US09401428B2
公开(公告)日：2016-07-26
申请号：US13795778
申请日：2013-03-12
申请人： Kyung-In Choi , Gyeom Kim , Hong-Sik Yoon , Bon-Young Koo , Wook-Je Kim
发明人： Kyung-In Choi , Gyeom Kim , Hong-Sik Yoon , Bon-Young Koo , Wook-Je Kim
IPC分类号： H01L29/76 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823821 , H01L29/66545 , H01L29/785 , H01L2924/13067
摘要： A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.
摘要翻译：半导体器件包括衬底上的栅极图案，栅极图案下方的跨越栅极图案的多通道有源图案，并且具有不与栅极图案重叠的第一区域和与栅极图案重叠的第二区域，多通道活性图案沿着第一区域的外周边并且包括具有浓度的杂质和多通道活性图案上的衬垫，衬垫在第一区域的侧表面上延伸并且不在第一区域的顶表面上延伸第一个地区。还描述了相关的制造方法。

2. 发明申请

US20120306004A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20120306004A1
公开(公告)日：2012-12-06
申请号：US13585119
申请日：2012-08-14
申请人： Hong Sik Yoon , Jinshi Zhao , Ingyu Baek , Hyun Jun Sim , Minyoung Park
发明人： Hong Sik Yoon , Jinshi Zhao , Ingyu Baek , Hyun Jun Sim , Minyoung Park
IPC分类号： H01L29/78
CPC分类号： H01L27/228 , H01L27/0207 , H01L27/2454 , H01L27/249
摘要： Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.
摘要翻译：提供了一种半导体存储器件。半导体存储器件可以包括在基本上垂直于半导体衬底的上表面的方向上延伸的局部位线和与局部位线相交的局部字线。局部位线电连接到贯穿位线晶体管的栅极的位线通道柱，并且本地字线电连接到贯穿字线晶体管的栅极的字线通道柱。

3. 发明申请

US20120061752A1 SINGLE TRANSISTOR FLOATING-BODY DRAM DEVICES HAVING VERTICAL CHANNEL TRANSISTOR STRUCTURES 失效
标题翻译：具有垂直通道晶体管结构的单晶体浮体体DRAM器件
公开(公告)号：US20120061752A1
公开(公告)日：2012-03-15
申请号：US13301254
申请日：2011-11-21
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L29/78
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.
摘要翻译：单晶体体浮体DRAM器件具有垂直沟道晶体管结构。 DRAM器件包括衬底，以及设置在衬底上并彼此隔离的第一和第二浮体。源极区域和漏极区域设置在第一和第二浮体的每一个之下和之上。栅电极设置在第一和第二浮体之间。还提供了制造单晶体管浮体DRAM器件的方法。

4. 发明授权

US07982318B2 Device including contact structure and method of forming the same 失效
标题翻译：包括接触结构的装置及其形成方法
公开(公告)号：US07982318B2
公开(公告)日：2011-07-19
申请号：US11655116
申请日：2007-01-19
申请人： Jang-Eun Heo , Young-Moon Choi , Sun-Woo Lee , Hong-Sik Yoon , Kyung-Rae Byun
发明人： Jang-Eun Heo , Young-Moon Choi , Sun-Woo Lee , Hong-Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/3212 , H01L21/76823 , H01L21/76825 , H01L21/76831 , H01L21/76867 , H01L21/76876 , H01L21/76879 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , H01L2924/00
摘要： A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.
摘要翻译：一种器件包括在具有下导电图案的衬底上的绝缘层，所述绝缘层具有穿透绝缘层并暴露一部分下导电图案的接触孔，催化图案具有第一部分在暴露部分上下导电图案和接触孔的侧壁上的第二部分，在接触孔的侧壁上的间隔件，其中催化剂图案的第二部分设置在间隔件和侧壁之间，接触插塞在接触孔中并使催化剂图案接触，所述接触塞是碳纳米管材料。

5. 发明授权

US07535778B2 Semiconductor memory device with memory cells, each having bit registering layer in addition to a memory layer and method of driving the same 有权
标题翻译：具有存储单元的半导体存储器件，每个都具有除存储器层之外的位对位层及其驱动方法
公开(公告)号：US07535778B2
公开(公告)日：2009-05-19
申请号：US11365585
申请日：2006-03-02
申请人： Hong-Sik Yoon , In-Seok Yeo
发明人： Hong-Sik Yoon , In-Seok Yeo
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C29/816 , G11C29/88 , G11C2213/77 , Y10S977/712
摘要： The semiconductor memory device includes a memory layer having a plurality of memory cells for storing data, and at least one bit registering layer for recording status information on whether the memory cells are defective. The memory layer may be a nanometer-scale memory device, such as a molecular memory, a carbon nanotube memory, an atomic memory, a single electron memory, or a memory fabricated by a chemical bottom-up method, etc.
摘要翻译：半导体存储器件包括具有用于存储数据的多个存储器单元的存储器层以及用于记录关于存储器单元是否有缺陷的状态信息的至少一个位寄存层。存储层可以是纳米级存储器件，例如分子存储器，碳纳米管存储器，原子存储器，单电子存储器或通过化学自下而上法制造的存储器等。

6. 发明授权

US07384841B2 DRAM device and method of manufacturing the same 失效
标题翻译： DRAM装置及其制造方法
公开(公告)号：US07384841B2
公开(公告)日：2008-06-10
申请号：US11358060
申请日：2006-02-22
申请人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
发明人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
IPC分类号： H01L21/8234 , H01L21/8244
CPC分类号： H01L27/10873 , H01L27/10829
摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.
摘要翻译：在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。非导电图案具有比导电图案的带隙大的带隙。在MTJ结构的侧壁上形成栅极绝缘层和栅电极。字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因此DRAM器件需要较小的衬底表面积。

7. 发明授权

US07338862B2 Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure 失效
标题翻译：制造具有凹槽沟道晶体管结构的单晶体管浮体DRAM单元的方法
公开(公告)号：US07338862B2
公开(公告)日：2008-03-04
申请号：US11335333
申请日：2006-01-19
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/7841 , H01L29/78648
摘要： Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region within the body layer. A recess region is formed in the floating body region. A gate electrode is formed in the recess region. Impurity ions of a first conductivity type are implanted into a portion of the floating body region on a first side of the recess region to define a source region and into a portion of the floating body on an opposite side of the recess region to define a drain region to provide a floating body.
摘要翻译：制造单晶体管浮体动态随机存取存储器（DRAM）单元的方法包括在半导体衬底上形成阻挡层。主体层形成在阻挡层上。形成隔离层，限定体层内的浮体区域。在浮体区域中形成有凹部。在凹陷区域中形成栅电极。第一导电类型的杂质离子注入到凹陷区域的第一侧上的浮体区域的一部分中，以限定源极区域并且在凹陷区域的相对侧上限定浮体的一部分以限定漏极区域提供浮体。

8. 发明申请

US20060197131A1 DRAM device and method of manufacturing the same 失效
标题翻译： DRAM装置及其制造方法
公开(公告)号：US20060197131A1
公开(公告)日：2006-09-07
申请号：US11358060
申请日：2006-02-22
申请人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
发明人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
IPC分类号： H01L29/94
CPC分类号： H01L27/10873 , H01L27/10829
摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.
摘要翻译：在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。非导电图案具有比导电图案的带隙大的带隙。在MTJ结构的侧壁上形成栅极绝缘层和栅电极。字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因此DRAM器件需要较小的衬底表面积。

9. 发明申请

US20100208508A1 Multi-level nonvolatile memory devices using variable resistive elements 有权
标题翻译：使用可变电阻元件的多级非易失性存储器件
公开(公告)号：US20100208508A1
公开(公告)日：2010-08-19
申请号：US12656754
申请日：2010-02-16
申请人： In-Gyu Baek , Hyun-Jun Sim , Hong-Sik Yoon , Jin-Shi Zhao , Min-Young Park
发明人： In-Gyu Baek , Hyun-Jun Sim , Hong-Sik Yoon , Jin-Shi Zhao , Min-Young Park
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0073 , G11C2211/5641 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.
摘要翻译：使用可变电阻元件的多级非易失性存储器件，多级非易失性存储器件包括字线，位线和耦合在字线和位线之间的多电平存储器单元，多电平存储器单元当施加具有相同极性的第一和第二写入偏置时，具有高于第一电阻电平的第一电阻电平和第二电阻电平，以及在第一和第二电阻电平之间范围内的第三电阻电平和第四电阻电平，当施加具有彼此不同极性的第三和第四写入偏置。

10. 发明申请

US20100155853A1 MULTIPLEXER AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：多路复用器及其制造方法
公开(公告)号：US20100155853A1
公开(公告)日：2010-06-24
申请号：US12641836
申请日：2009-12-18
申请人： Hong-Sik Yoon
发明人： Hong-Sik Yoon
IPC分类号： H01L27/105 , H03K17/00 , H01L21/77
CPC分类号： G11C7/1006 , G11C7/1012
摘要： A multiplexer can include a signal line arranged on a substrate and including a plurality of data wires extending in a first direction and electrically insulated from one another, where each of the data wires has at least one recess to provide at least two data wiring pieces. An address line is arranged on the signal line and includes a plurality of coding lines extending in a second direction different from the first direction and electrically insulated from the data wires. A plurality of switching elements are positioned in the recesses of the data wires and make electrical contact with the coding lines, where the switching element is configured to switch a data signal applied to the data wiring on and off in accordance with a coding signal applied to the coding lines, so that one of the data wires is selected according to a binary code of the address line corresponding to combinations of the coding lines to which coding signal is applied.
摘要翻译：多路复用器可以包括布置在基板上的信号线，并且包括在第一方向上延伸并且彼此电绝缘的多条数据线，其中每条数据线具有至少一个凹部以提供至少两条数据布线片。地址线布置在信号线上，并且包括沿与第一方向不同的第二方向延伸并与数据线电绝缘的多条编码线。多个开关元件位于数据线的凹部中并与编码线电接触，其中开关元件被配置为根据施加到数据线的编码信号来接通和断开施加到数据线的数据信号编码线，使得根据与应用了编码信号的编码线的组合对应的地址线的二进制码来选择数据线之一。

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