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1. 发明申请

US20110264990A1 VERIFYING THE ERROR BOUND OF NUMERICAL COMPUTATION IMPLEMENTED IN COMPUTER SYSTEMS 失效
标题翻译：验证计算机系统中实现的数值计算的误差
公开(公告)号：US20110264990A1
公开(公告)日：2011-10-27
申请号：US12766163
申请日：2010-04-23
申请人： Jun Sawada
发明人： Jun Sawada
IPC分类号： G06F11/07
CPC分类号： G06F11/3608
摘要： A verification tool receives a finite precision definition for an approximation of an infinite precision numerical function implemented in a processor in the form of a polynomial of bounded functions. The verification tool receives a domain for verifying outputs of segments associated with the infinite precision numerical function. The verification tool splits the domain into at least two segments, wherein each segment is non-overlapping with any other segment and converts, for each segment, a polynomial of bounded functions for the segment to a simplified formula comprising a polynomial, an inequality, and a constant for a selected segment. The verification tool calculates upper bounds of the polynomial for the at least two segments, beginning with the selected segment and reports the segments that violate a bounding condition.
摘要翻译：验证工具接收有限精度定义，用于以有界函数的多项式的形式在处理器中实现的无限精度数值函数的近似。验证工具接收用于验证与无限精度数值函数相关联的段的输出的域。验证工具将域分成至少两个段，其中每个段与任何其他段不重叠，并且对于每个段将用于该段的有界函数的多项式转换为包括多项式，不等式和所选段的常数。验证工具从所选择的段开始计算至少两个段的多项式的上限，并报告违反边界条件的段。

2. 发明申请

US20090177870A1 Method and System for a Wiring-Efficient Permute Unit 失效
标题翻译：一种有效的宽带单元的方法和系统
公开(公告)号：US20090177870A1
公开(公告)日：2009-07-09
申请号：US11968692
申请日：2008-01-03
申请人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
发明人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
IPC分类号： G06F9/305 , G06F13/00
CPC分类号： G06F9/30032 , G06F7/762 , G06F7/766 , G06F9/30036 , G06F9/3824 , G06F9/3826
摘要： A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
摘要翻译：一种在置换单元中提供布线效率的方法。多个选择器从多个寄存器文件接收输入数据和共享控制信号。置换单元包括耦合到多个逻辑与门的多个多路复用器（MUX）。多个逻辑与门被耦合到多个逻辑或门。逻辑“与”门与逻辑或门物理分离。逻辑与门接收来自选择器的一个或多个输出数据信号的输入。逻辑或门组合来自逻辑与门的一个或多个输出信号，并提供来自置换单元的输出数据。

3. 发明授权

US07272624B2 Fused booth encoder multiplexer 失效
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US07272624B2
公开(公告)日：2007-09-18
申请号：US10675674
申请日：2003-09-30
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

4. 发明申请

US20050239440A1 Replaceable sequenced one-time pads for detection of cloned service client 失效
标题翻译：可替换的顺序一次性检测克隆服务客户端
公开(公告)号：US20050239440A1
公开(公告)日：2005-10-27
申请号：US10829571
申请日：2004-04-22
申请人： Yen-Fu Chen , John Handy-Bosma , Jun Sawada , Mei Selvage , Keith Walker
发明人： Yen-Fu Chen , John Handy-Bosma , Jun Sawada , Mei Selvage , Keith Walker
IPC分类号： H04L29/06 , H04M1/66 , H04W12/12
CPC分类号： H04L63/0838 , H04L63/0853 , H04W12/06 , H04W12/12
摘要： A client device authenticated a one-time pad table stored in the client device, and a matching table maintained by a service provider. When a request for service is posted from the client to the service provider, the next unused pad is exchanged and verified with the current state of the service provider's copy of the table. If the OTP is the next unused code, service is granted, else the user is challenged to identify himself, which when successfully completed results in the client device being downloaded with a new OTP table, replacing the compromised table. Use of service by a cloned device causes the OTP table at the service provider to become out of synchronization with the authentic device's copy of the table, thereby setting up the ability to detect the fraud, stop the service consumption by the clone, and reprogram the authentic device to allow for uninterrupted service.
摘要翻译：客户端设备认证存储在客户端设备中的一次性填充表，以及由服务提供商维护的匹配表。当从客户端向服务提供商发布服务请求时，下一个未使用的邮箱将与服务提供商的表副本的当前状态进行交换和验证。如果OTP是下一个未使用的代码，则授予服务，否则用户将面临挑战，即自己识别，当成功完成导致客户端设备正在使用新的OTP表进行下载时，替换受损表。使用克隆设备的服务会导致服务提供商的OTP表与正版设备的表副本不同步，从而设置检测到欺诈的能力，停止克隆的服务消耗，并重新编程真实的设备，允许不间断的服务。

5. 发明授权

US08756543B2 Verifying data intensive state transition machines related application 失效
标题翻译：验证数据密集型状态转换机相关应用
公开(公告)号：US08756543B2
公开(公告)日：2014-06-17
申请号：US13097171
申请日：2011-04-29
申请人： Viresh Paruthi , Peter Anthony Sandon , Jun Sawada
发明人： Viresh Paruthi , Peter Anthony Sandon , Jun Sawada
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504 , G06F9/4498 , G06F17/5022
摘要： A method, system, and computer program product for verification of a state transition machine (STM) are provided in the illustrative embodiments. The STM representing the operation of a circuit configured to perform a computation is received. A segment of the STM is selected from a set of segments of the STM. A set of properties of the segment is determined. The set of properties is translated into a hardware description to form a translation. The segment is verified by verifying whether all relationships between a pre-condition and a post condition in the translation hold true for any set of inputs and any initial state of a hardware design under test. A verification result for the segment is generated. Verification results for each segment in the set of segments are combined to generate a verification result for the STM.
摘要翻译：在说明性实施例中提供了用于验证状态转换机（STM）的方法，系统和计算机程序产品。接收表示被配置为执行计算的电路的操作的STM。从STM的一组段中选择STM的一段。确定该段的一组属性。该属性集被翻译成硬件描述以形成一个翻译。通过验证翻译中的前提条件和后期条件之间的所有关系是否适用于任何一组输入以及所测试的硬件设计的任何初始状态来验证该段。生成段的验证结果。组合段中每个段的验证结果，以生成STM的验证结果。

6. 发明授权

US08641332B2 Process for machining pressure detection hole and apparatus for machining pressure detection hole 有权
标题翻译：压力检测孔加工过程及加压检测孔加工装置
公开(公告)号：US08641332B2
公开(公告)日：2014-02-04
申请号：US12942306
申请日：2010-11-09
申请人： Kaneyoshi Hiraga , Jun Sawada
发明人： Kaneyoshi Hiraga , Jun Sawada
IPC分类号： B23B35/00 , B23B41/00
CPC分类号： B23Q17/2409 , Y10T408/03 , Y10T408/08 , Y10T408/21 , Y10T408/553 , Y10T408/5617
摘要： A pressure detection passage and a side edge of a pressure detection member are positioned for a tip of a stylus attached to a drilling device by holding the pressure detection member on a hand-operated stage and moving the pressure detection member in the X axis direction by a micrometer head of the hand-operated stage while checking an enlarged image picked up by a microscope and displayed on a monitor, and a personal computer stores positions of the side edge of the pressure detection member and the pressure detection passage which are measured by scales of the micrometer head. Subsequently, the stylus is exchanged for a drill and the drilling device is moved down by a micrometer head for moving up and down a slider, while moving in sequence in the X axis direction the hand-operated stage by operating the micrometer head of the hand-operated stage so as to reappear the position stored in the personal computer, thereby drilling in the pressure detection member pressure detection holes communicating with the respective pressure detection passages. Therefore, it is possible to improve the precision and ease of operation of drilling a pressure detection hole in a pressure detection member.
摘要翻译：通过将压力检测部件保持在手动工作台上并将压力检测部件沿X轴方向移动而将压力检测部件和压力检测部件的侧缘定位用于安装在钻孔装置上的触针的尖端，在检查由显微镜拾取的放大图像并显示在监视器上时，手动台的千分尺头部，并且个人计算机存储压力检测构件和压力检测通道的侧面的位置，该位置由鳞片测量的千分尺头。随后，将触针更换为钻头，并且钻头装置通过用于在滑块上下移动的测微头向下移动，同时通过操作手指的千分尺来在X轴方向上依次移动手动操作台以再现存储在个人计算机中的位置，从而在与各个压力检测通道连通的压力检测构件压力检测孔中钻孔。因此，可以提高压力检测部件中的压力检测孔的钻孔的精度和操作的容易性。

7. 发明授权

US08397189B2 Model checking in state transition machine verification 有权
标题翻译：状态转换机器验证中的模型检查
公开(公告)号：US08397189B2
公开(公告)日：2013-03-12
申请号：US13097193
申请日：2011-04-29
申请人： Viresh Paruthi , Peter Anthony Sandon , Jun Sawada
发明人： Viresh Paruthi , Peter Anthony Sandon , Jun Sawada
IPC分类号： G06F9/455
CPC分类号： G06F17/504
摘要： A method, system, and computer program product for improved model checking for verification of a state transition machine (STM) are provided. A hardware design under test and a property to be verified are received. A level (k) of induction proof needed for the verification is determined. A circuit representation of the property using the hardware design under test for k base cases is configured for checking that the circuit representation holds true for the property for each of the k base cases, and for testing an induction without hypothesis by testing whether the property holds true after k clock cycles starting from a randomized state, where induction without hypothesis is performed by omitting a test whether the property holds true for the next cycle after the property holds for k successive cycles. The induction proof of the property using the hardware design under test by induction without hypothesis is produced.
摘要翻译：提供了一种用于改进状态转换机（STM）验证的模型检查的方法，系统和计算机程序产品。收到被测试的硬件设计和待验证的属性。确定验证所需的感应等级（k）。配置用于k个基本情况的使用被测硬件设计的属性的电路表示被配置用于检查电路表示对于每个k个基本情况的属性是否成立，以及通过测试属性是否保持来测试没有假设的感应在从随机化状态开始的k个时钟周期之后为真，其中通过省略在k个连续循环的该属性成立后的下一个周期的属性是否成立的情况下执行无假设的诱导。产生使用通过没有假设的感应的被测硬件设计的属性的感应证明。

8. 发明授权

US08181134B2 Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design 有权
标题翻译：用于执行集成电路逻辑设计的条件顺序等价性检查的技术
公开(公告)号：US08181134B2
公开(公告)日：2012-05-15
申请号：US12580373
申请日：2009-10-16
申请人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Jun Sawada
发明人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Jun Sawada
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for conditional sequential equivalence checking of logic designs embodied in netlists includes creating an equivalence-checking netlist over a first netlist and a second netlist. The conditional sequential equivalence checking includes conditions under which equivalences of the first and second netlists are checked. The technique derives a set of candidate conditional equivalence invariants for each correlated gate in a correlated gate pair set and attempts to prove that each candidate conditional equivalence invariant in the set of candidate conditional equivalence invariants is accurate. The candidate conditional equivalence invariants that cannot be proven accurate are removed from the set of candidate conditional equivalence invariants. The candidate conditional equivalence invariants that have been proven accurate are recorded as a set of conditional equivalence invariants. Finally, the conditional sequential equivalence checking of the equivalence-checking netlist is completed using the set of conditional equivalence invariants that are recorded.
摘要翻译：用于在网表中体现的逻辑设计的条件顺序等价检查的技术包括在第一网表和第二网表上创建等价检查网表。条件顺序等价检查包括检查第一和第二网表的等价物的条件。该技术为相关门对集合中的每个相关门导出一组候选条件等价不变量，并尝试证明候选条件等价不变量集合中的每个候选条件等价不变量是准确的。从候选条件等价不变量集合中删除不能被证明是准确的候选条件等价不变量。已被证明是准确的候选条件等价不变量被记录为一组条件等价不变量。最后，使用记录的条件等价不变量集来完成等价检查网表的条件序列等价性检查。

9. 发明申请

US20110093824A1 TECHNIQUES FOR PERFORMING CONDITIONAL SEQUENTIAL EQUIVALENCE CHECKING OF AN INTEGRATED CIRCUIT LOGIC DESIGN 有权
标题翻译：执行集成电路逻辑设计的条件顺序等价检查技术
公开(公告)号：US20110093824A1
公开(公告)日：2011-04-21
申请号：US12580373
申请日：2009-10-16
申请人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Jun Sawada
发明人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Jun Sawada
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for conditional sequential equivalence checking of logic designs embodied in netlists includes creating an equivalence-checking netlist over a first netlist and a second netlist. The conditional sequential equivalence checking includes conditions under which equivalences of the first and second netlists are checked. The technique derives a set of candidate conditional equivalence invariants for each correlated gate in a correlated gate pair set and attempts to prove that each candidate conditional equivalence invariant in the set of candidate conditional equivalence invariants is accurate. The candidate conditional equivalence invariants that cannot be proven accurate are removed from the set of candidate conditional equivalence invariants. The candidate conditional equivalence invariants that have been proven accurate are recorded as a set of conditional equivalence invariants. Finally, the conditional sequential equivalence checking of the equivalence-checking netlist is completed using the set of conditional equivalence invariants that are recorded.
摘要翻译：用于在网表中体现的逻辑设计的条件顺序等价检查的技术包括在第一网表和第二网表上创建等价检查网表。条件顺序等价检查包括检查第一和第二网表的等价物的条件。该技术为相关门对集合中的每个相关门导出一组候选条件等价不变量，并尝试证明候选条件等价不变量集合中的每个候选条件等价不变量是准确的。从候选条件等价不变量集合中删除不能被证明是准确的候选条件等价不变量。已被证明是准确的候选条件等价不变量被记录为一组条件等价不变量。最后，使用记录的条件等价不变量集来完成等价检查网表的条件序列等价性检查。

10. 发明授权

US07383480B2 Scanning latches using selecting array 失效
标题翻译：使用选择阵列扫描锁存器
公开(公告)号：US07383480B2
公开(公告)日：2008-06-03
申请号：US10896505
申请日：2004-07-22
申请人： Andrew Kenneth Martin , Chandler Todd McDowell , Robert Kevin Montoye , Jun Sawada
发明人： Andrew Kenneth Martin , Chandler Todd McDowell , Robert Kevin Montoye , Jun Sawada
IPC分类号： G01R31/28
CPC分类号： G11C29/32 , G01R31/318572 , G11C11/41 , G11C2029/3202
摘要： A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.
摘要翻译：一种用于从锁存器的矩阵阵列中的特定锁存器扫描数据的方法和系统。矩阵阵列由垂直选择线和水平数据线组成。每个锁存器通过晶体管耦合在选择器线和数据线的交叉点处。通过接通晶体管，可以选择性地读取或写入锁存器的内容。

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