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1. 发明授权

US07272624B2 Fused booth encoder multiplexer 失效
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US07272624B2
公开(公告)日：2007-09-18
申请号：US10675674
申请日：2003-09-30
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

2. 发明授权

US09274751B2 Fused booth encoder multiplexer 有权
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US09274751B2
公开(公告)日：2016-03-01
申请号：US11776454
申请日：2007-07-11
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/533 , G06F7/483 , G06F7/544
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

3. 发明授权

US08229992B2 Fused booth encoder multiplexer 失效
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US08229992B2
公开(公告)日：2012-07-24
申请号：US11670357
申请日：2007-02-01
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

4. 发明授权

US06891399B2 Variable pulse width and pulse separation clock generator 失效
标题翻译：可变脉冲宽度和脉冲分离时钟发生器
公开(公告)号：US06891399B2
公开(公告)日：2005-05-10
申请号：US10388977
申请日：2003-03-13
申请人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
发明人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
IPC分类号： G06F1/08 , H03K5/159 , H03K7/08 , H03K19/00 , G06F1/04 , H03H11/26 , H03K3/00
CPC分类号： G06F1/08 , H03K5/159 , H03K7/08
摘要： A clock pulse generator for generating at least two clocked pulse signals from a global clock signal is provided. The clock pulse generator includes at least one input for receiving a clock signal having a rising and a falling edge and a mechanism for selectably delaying a rising edge of a pulse signal synchronized to the falling edge of the clock signal. The clock pulse generator further includes a first selectable duration pulse synchronized to the rising edge of the clock signal and a second selectable duration pulse synchronized to the selectably delayed rising edge. The clock pulse generator also includes a glitch avoidance circuit to remove glitches in the clock signal before it is used.
摘要翻译：提供了一种用于从全局时钟信号产生至少两个时钟脉冲信号的时钟脉冲发生器。时钟脉冲发生器包括用于接收具有上升沿和下降沿的时钟信号的至少一个输入端和用于可选地延迟与时钟信号的下降沿同步的脉冲信号的上升沿的机构。时钟脉冲发生器还包括与时钟信号的上升沿同步的第一可选择持续时间脉冲和与可选择地延迟的上升沿同步的第二可选择持续时间脉冲。时钟脉冲发生器还包括一个毛刺回避电路，用于消除时钟信号使用前的毛刺。

5. 发明授权

US06650145B2 Circuits and systems for limited switch dynamic logic 失效
标题翻译：有限开关动态逻辑的电路和系统
公开(公告)号：US06650145B2
公开(公告)日：2003-11-18
申请号：US10116612
申请日：2002-04-04
申请人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
发明人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
IPC分类号： H03K1900
CPC分类号： H03K19/0963
摘要： Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.
摘要翻译：用于在动态逻辑器件的输出线上产生静态开关因子的电路和系统。实现具有动态部分和静态部分的逻辑设备。这样，只要设备执行的布尔运算的值不变，就保持输出逻辑状态。此外，静态逻辑元件可以执行输出逻辑感应所需的反转，减轻提供双轨动态逻辑实现的需要。非对称时钟允许预充电晶体管的尺寸伴随减小，因此改善了逻辑元件所需的面积，并且避免了对保持器装置的需要。

6. 发明授权

US07282960B2 Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock 失效
标题翻译：具有由电压非对称时钟分别控制的预充电元件的动态逻辑电路
公开(公告)号：US07282960B2
公开(公告)日：2007-10-16
申请号：US11168718
申请日：2005-06-28
申请人： Wendy Ann Belluomini , Robert Kevin Montoye , Aniket Mukul Saha
发明人： Wendy Ann Belluomini , Robert Kevin Montoye , Aniket Mukul Saha
IPC分类号： H03K19/20 , H03K19/094 , H03K19/0175 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.
摘要翻译：具有由电压非对称时钟控制的预充电元件的动态逻辑电路在动态数字电路中提供了增强的抗噪声能力。通过对具有减小预充电元件的电压方向上的摆幅减小的信号对预充电元件进行计时，预充电元件提供小电流，以防止门的动态求和节点由于噪音，并且消除了对保持装置的需要。将降频摆动非对称时钟提供为单独的信号可防止电路其余部分的性能下降。具体地说，利用全摆动时钟来控制电路的动态部分中的脚部装置，使得评估不会受到噪声的影响或减慢。电路的任何静态部分中的脚踏和上拉器件也可以通过全频时钟控制，从而不影响开关速度和漏电抗扰度。

7. 发明授权

US08276041B2 Data integrity validation using hierarchical volume management 有权
标题翻译：使用分层卷管理的数据完整性验证
公开(公告)号：US08276041B2
公开(公告)日：2012-09-25
申请号：US12269123
申请日：2008-11-12
申请人： James Lee Hafner , Wendy Ann Belluomini , Douglas William Dewey , Brian D. McKean , Donald R. Humlicek , Kevin L. Kidney , Theresa L. Segura
发明人： James Lee Hafner , Wendy Ann Belluomini , Douglas William Dewey , Brian D. McKean , Donald R. Humlicek , Kevin L. Kidney , Theresa L. Segura
IPC分类号： G11C29/00
CPC分类号： G06F12/0866 , G06F11/1008 , G06F11/1076
摘要： A method for reading data from a data storage system is provided. The method comprises requesting a virtual data volume to access data from one or more data blocks in the data storage system; requesting a virtual protection information volume to access protection information associated with the data blocks; validating the data using the protection information; and providing the data to the host interface, in response to successful validation of the data. A method for writing data to a data storage system is also provided. The method comprises receiving data to be written to one or more data blocks in the data storage system, wherein the data is stored in a cache; generating protection information to be stored on a virtual protection information volume; requesting a virtual data volume to update the data blocks with the data; and requesting the virtual protection information volume to store the protection information.
摘要翻译：提供了一种从数据存储系统读取数据的方法。该方法包括：请求虚拟数据卷从数据存储系统中的一个或多个数据块访问数据; 请求虚拟保护信息量来访问与数据块相关联的保护信息; 使用保护信息验证数据; 并且响应于数据的成功验证，将数据提供给主机接口。还提供了一种将数据写入数据存储系统的方法。该方法包括接收要写入数据存储系统中的一个或多个数据块的数据，其中数据被存储在高速缓存中; 产生要存储在虚拟保护信息量上的保护信息; 请求虚拟数据卷用数据更新数据块; 并请求虚拟保护信息量来存储保护信息。

8. 发明授权

US07598774B2 Reduced power consumption limited-switch dynamic logic (LSDL) circuit 失效
标题翻译：降低功耗限流开关动态逻辑（LSDL）电路
公开(公告)号：US07598774B2
公开(公告)日：2009-10-06
申请号：US12145715
申请日：2008-06-25
申请人： Wendy Ann Belluomini , Aniket Mukul Saha
发明人： Wendy Ann Belluomini , Aniket Mukul Saha
IPC分类号： H03K19/20 , H03K19/094 , H03K3/356
CPC分类号： H03K19/0016
摘要： An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.
摘要翻译：有限开关动态逻辑（LSDL）电路通过降低时钟功耗来降低功耗。通过在评估阶段对具有降低的电压摆幅的时钟信号对LSDL门进行时钟控制，允许LSDL栅极工作，同时显着降低时钟功耗。由于时钟功耗主导于LSDL电路，因此时钟功耗的降低导致整体电路功耗的显着降低。通过向本地时钟缓冲器提供额外的电源轨，在多个本地时钟缓冲器产生减小的摆动时钟，该额外的电源轨响应于从本地时钟缓冲器接收到的全摆幅评估相位时钟而被本地时钟缓冲器切换到时钟分配线全局时钟分配网络由本地时钟缓冲区。

9. 发明授权

US07047468B2 Method and apparatus for low overhead circuit scan 失效
标题翻译：低开销电路扫描的方法和装置
公开(公告)号：US07047468B2
公开(公告)日：2006-05-16
申请号：US10670832
申请日：2003-09-25
申请人： Wendy Ann Belluomini , Andrew K. Martin , Chandler Todd McDowell , Robert Kevin Montoye
发明人： Wendy Ann Belluomini , Andrew K. Martin , Chandler Todd McDowell , Robert Kevin Montoye
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G11C29/003
摘要： A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of a group of cascaded latches where there are insufficient extra state holding elements in the group to enable normal scan. A multiplicity of local scan clocks are utilized to shift selected amounts of data only when a next state holding element in the group has been made available by clearing the contents of that next state holding element. In this way, any given latch, for the purpose of scan, is not a dedicated master or slave latch, but can act as either. This invention also addresses a circuit for the creation of the multiplicity of local clocks from a conventional LSSD clock source.
摘要翻译：用于在保持元素数组的状态下操作数据的方法和系统。过程控制器将过程数据移动通过状态保持元素数组。单独的扫描控制器通过从组中不充足的额外状态保持元件的一组级联锁存器扫描数据来扫描状态保持元件阵列中的数据，以启用正常扫描。仅当通过清除该下一状态保持元件的内容已经使该组中的下一状态保持元件可用时，才使用多个本地扫描时钟来移位所选择的数据量。以这种方式，为了扫描的目的，任何给定的锁存器不是专用的主器件或从器件锁存器，而是可以作为任一个。本发明还涉及用于从常规LSSD时钟源产生多个本地时钟的电路。

10. 发明申请

US20100122055A1 DATA INTEGRITY VALIDATION USING HIERARCHICAL VOLUME MANAGEMENT 有权
标题翻译：使用分层体积管理的数据完整性验证
公开(公告)号：US20100122055A1
公开(公告)日：2010-05-13
申请号：US12269123
申请日：2008-11-12
申请人： James Lee Hafner , Wendy Ann Belluomini , Douglas William Dewey , Brian D. McKean , Donald R. Humlicek , Kevin L. Kidney , Theresa L. Segura
发明人： James Lee Hafner , Wendy Ann Belluomini , Douglas William Dewey , Brian D. McKean , Donald R. Humlicek , Kevin L. Kidney , Theresa L. Segura
IPC分类号： G06F12/14
CPC分类号： G06F12/0866 , G06F11/1008 , G06F11/1076
摘要： A method for reading data from a data storage system is provided. The method comprises requesting a virtual data volume to access data from one or more data blocks in the data storage system; requesting a virtual protection information volume to access protection information associated with the data blocks; validating the data using the protection information; and providing the data to the host interface, in response to successful validation of the data. A method for writing data to a data storage system is also provided. The method comprises receiving data to be written to one or more data blocks in the data storage system, wherein the data is stored in a cache; generating protection information to be stored on a virtual protection information volume; requesting a virtual data volume to update the data blocks with the data; and requesting the virtual protection information volume to store the protection information.
摘要翻译：提供了一种从数据存储系统读取数据的方法。该方法包括：请求虚拟数据卷从数据存储系统中的一个或多个数据块访问数据; 请求虚拟保护信息量来访问与数据块相关联的保护信息; 使用保护信息验证数据; 并且响应于数据的成功验证，将数据提供给主机接口。还提供了一种将数据写入数据存储系统的方法。该方法包括接收要写入数据存储系统中的一个或多个数据块的数据，其中数据被存储在高速缓存中; 产生要存储在虚拟保护信息量上的保护信息; 请求虚拟数据卷用数据更新数据块; 并请求虚拟保护信息量来存储保护信息。

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