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1. 发明授权

US4965769A Semiconductor memory capable of high-speed data erasing 失效
标题翻译：具有高速数据擦除功能的半导体存储器
公开(公告)号：US4965769A
公开(公告)日：1990-10-23
申请号：US278025
申请日：1988-11-30
申请人： Jun Etoh , Kiyoo Itoh , Masakazu Aoki , Ryoichi Hori
发明人： Jun Etoh , Kiyoo Itoh , Masakazu Aoki , Ryoichi Hori
IPC分类号： G11C11/401 , G11C7/20 , G11C8/12 , G11C11/404 , G11C11/4072 , G11C11/408 , H01L27/10
CPC分类号： G11C7/20 , G11C11/4072 , G11C11/4087 , G11C8/12
摘要： A semiconductor memory having a plurality of word lines, and a plurality of data lines arranged to intersect the word lines. Memory cells are arranged at nodes of the word lines and the data lines. Each of the memory cells has a field effect transistor and a capacitor. A word line multiple selection circuit is provided for selecting a plurality of the word lines. The multiple selection circuit simultaneously accesses all of the memory cells by selecting all the word lines of a memory array when a semiconductor memory is in a clear mode. In the clear mode a detector selects data lines of the memory array. A plate voltage control circuit controls a voltage at one plate of each of the capacitors in the memory cells. The plate control circuit changes a voltage at the plate to a preselected clear mode voltage when a semiconductor memory is in a clear mode. It is a feature of the invention that preselected data is written in the memory cells by data communication through the data lines during the clear mode. The preselected data includes at least one "1" data of the preselected data written in the memory cells. Subsequently to end the clear mode operation, the plate voltage control circuit changes the plate voltage for normal operations.
摘要翻译：一种具有多个字线的半导体存储器和与该字线相交的多条数据线。存储单元被布置在字线和数据线的节点处。每个存储单元都具有场效应晶体管和电容器。提供用于选择多个字线的字线多重选择电路。当半导体存储器处于清除模式时，多选择电路通过选择存储器阵列的所有字线来同时访问所有存储单元。在清除模式下，检测器选择存储器阵列的数据线。板电压控制电路控制存储单元中的每个电容器的一个板上的电压。当半导体存储器处于清除模式时，板控制电路将板处的电压改变为预选的清除模式电压。本发明的特征在于，在清除模式期间，通过数据线进行数据通信，将预选数据写入存储单元。预选数据包括写入存储单元的预选数据的至少一个“1”数据。随后结束清除模式操作，板电压控制电路改变正常操作的板电压。

2. 发明授权

US5614847A Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US5614847A
公开(公告)日：1997-03-25
申请号：US294055
申请日：1994-08-24
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20 , H03K19/0948
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

3. 发明授权

US5272393A Voltage converter of semiconductor device 失效
标题翻译：半导体器件的电压转换器
公开(公告)号：US5272393A
公开(公告)日：1993-12-21
申请号：US790065
申请日：1991-11-12
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , H03K3/01 , H03K5/22
CPC分类号： H03K17/693 , G05F1/465
摘要： In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.
摘要翻译：在设置在半导体器件中的电压转换器中并向半导体器件中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。当半导体器件处于标准操作状态时，另一个电路选择第一电压，并且当器件处于另一种操作状态（例如测试或老化）时选择第二电压。所选择的电压可以由由P沟道MOS晶体管的负载和源极耦合的N沟道MOS晶体管对构成的差分放大器来转换。差分放大器的输出通过直接耦合的降压电路反馈，该电路产生转换的输出。

4. 发明授权

US5528548A Voltage converter of semiconductor device 失效
标题翻译：半导体器件的电压转换器
公开(公告)号：US5528548A
公开(公告)日：1996-06-18
申请号：US384962
申请日：1995-02-07
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , G11C7/00
CPC分类号： H03K17/693 , G05F1/465
摘要： A semiconductor memory is provided which includes a voltage converter supplying an internal supply voltage in proportion to the greater one of two reference voltages to a circuit in the semiconductor memory. The voltage converter includes a circuit which is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as a voltage dividing circuit. The memory also includes a word line booster for boosting the internal supply voltage.
摘要翻译：提供一种半导体存储器，其包括电压转换器，其向半导体存储器中的电路提供与两个参考电压中的较大一个成比例的内部电源电压。电压转换器包括电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一电路用于产生对外部供电电压的依赖性大于第一电压的依赖性。电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压电路。该存储器还包括用于升高内部电源电压的字线升压器。

5. 发明授权

US5880604A Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US5880604A
公开(公告)日：1999-03-09
申请号：US714994
申请日：1996-09-17
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20 , H03K19/0948 , H03K19/096
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

6. 发明授权

US6107836A Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US6107836A
公开(公告)日：2000-08-22
申请号：US199199
申请日：1998-11-25
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

7. 发明授权

US5617365A Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US5617365A
公开(公告)日：1997-04-01
申请号：US535574
申请日：1995-09-27
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the memory array is divided into memory mats. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there are provided, address comparing circuits each of which storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address, and selection circuitry including logical OR gates for replacing a defective bit line by a spare bit line in accordance with the result of the comparison. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
摘要翻译：引入冗余技术用于半导体存储器，更具体地，涉及具有16兆位或更多存储容量的动态随机存取存储器（DRAM）的冗余技术。在这样的DRAM中，存储器阵列被分成存储器垫。根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于提供两级交叉口中的期望的和备用位线，提供地址比较电路，每个存储器存储存储器阵列中存在的缺陷地址，并将要访问的地址与存储的缺陷地址进行比较，以及选择电路包括用于根据比较结果用备用位线替换有缺陷位线的逻辑“或”门。每个地址比较电路在其中存储有缺陷位线的列地址和指示与有缺陷位线对应的存储器堆的行地址的一部分。

8. 发明授权

US5426616A Semiconductor IC device having a voltage conversion circuit which generates an internal supply voltage having value compensated for external supply voltage variations 失效
标题翻译：具有电压转换电路的半导体IC器件，其产生补偿了外部电源电压变化的值的内部电源电压
公开(公告)号：US5426616A
公开(公告)日：1995-06-20
申请号：US243100
申请日：1994-05-16
申请人： Kazuhiko Kajigaya , Tetsu Udagawa , Kyoko Ishii , Manabu Tsunozaki , Kazuyoshi Oshima , Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Shin'ichi Ikenaga , Kiyoo Itoh
发明人： Kazuhiko Kajigaya , Tetsu Udagawa , Kyoko Ishii , Manabu Tsunozaki , Kazuyoshi Oshima , Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Shin'ichi Ikenaga , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C11/4074 , G11C29/50 , G11C11/407
CPC分类号： G11C29/028 , G11C11/4074 , G11C29/50 , G11C5/147 , G11C11/401 , G11C2029/5004 , Y10T307/344 , Y10T307/615 , Y10T307/62 , Y10T307/696
摘要： A voltage conversion circuit of the present invention is equipped with means for generating a first voltage stabilized with respect to ground potential of a semiconductor integrated circuit device including the circuit, means for generating second voltage stabilized with respect to an external supply voltage of the semiconductor integrated circuit device, and selection means for selecting either the first voltage or the second voltage. The first voltage age, stabilized with respect to the ground potential, is selected and used as the voltage at the time of normal operation, and the second voltage, stabilized with respect to the external supply voltage, is selected and used at the time of aging test. In this case, means for trimming the first voltage and/or the second voltage is, preferably, provided to raise the voltage accuracy.
摘要翻译：本发明的电压转换电路配备有用于产生相对于包括该电路的半导体集成电路器件的接地电位稳定的第一电压的装置，用于产生相对于半导体集成的外部电源电压稳定的第二电压的装置电路装置和用于选择第一电压或第二电压的选择装置。选择相对于地电位稳定的第一电压时间，并将其用作正常操作时的电压，并且在老化时选择并使用相对于外部电源电压稳定的第二电压测试。在这种情况下，优选地提供用于修整第一电压和/或第二电压的装置以提高电压精度。

9. 发明申请

US20050219922A1 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US20050219922A1
公开(公告)日：2005-10-06
申请号：US11139513
申请日：2005-05-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：用于制造存储器件的方法，所述存储器是具有备用位线的存储器阵列，并且提供具有冗余电路的缺陷恢复方案。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

10. 发明授权

US5179539A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5179539A
公开(公告)日：1993-01-12
申请号：US865677
申请日：1992-04-08
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02
CPC分类号： G11C5/147 , G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

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