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1. 发明授权

US5233237A BICMOS output buffer noise reduction circuit 失效
标题翻译： BICMOS输出缓冲器噪声减少电路
公开(公告)号：US5233237A
公开(公告)日：1993-08-03
申请号：US803466
申请日：1991-12-06
申请人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
发明人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
IPC分类号： H03K17/16 , H03K17/567 , H03K19/003 , H03K19/08 , H03K19/088 , H03K19/0944
CPC分类号： H03K19/00361 , H03K19/09448
摘要： A BICMOS output buffer circuit delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). A CMOS output pulldown driver transistor (Q60) sources base drive current to a relatively large current conducting bipolar primary output pulldown transistor (Q44). A relatively small current conducting CMOS secondary output pulldown transistor (Q60A) is coupled with primary current path in parallel with the primary current path of the bipolar primary output pulldown transistor (Q44) between the output (V.sub.OUT) and low potential power rail (GNDN). The control gate node of CMOS secondary output pulldown transistor (Q60A) is coupled to the control gate node of the CMOS output pulldown driver transistor (Q60) to initiate pulldown of a small sinking current before turn on of the bipolar primary output pulldown transistor (Q44) to reduce the maximum peak output noise (V.sub.OLP). A feed forward circuit capacitance is coupled between the control gate node of the CMOS output pulldown driver transistor (Q60) and base node of the bipolar output pulldown transistor (Q 44). The capacitance value is selected to pass a transient capacitive current sufficient for early turn on of the bipolar output pulldown transistor before the CMOS output pulldown driver transistor delivers sustained conduction current to reduce the maximum "valley" output noise (V.sub.OLV).

2. 发明授权

US5644460A Multi-rail electrostatic discharge protection device 失效
标题翻译：多轨静电放电保护装置
公开(公告)号：US5644460A
公开(公告)日：1997-07-01
申请号：US647274
申请日：1996-05-13
申请人： Stephen W. Clukey
发明人： Stephen W. Clukey
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0248 , H01L27/0251 , H01L27/0259
摘要： Device for protecting against circuit-damaging voltage spikes at input nodes and output nodes of electrical circuits and between high- and low-potential power rails. The voltage spikes are of the type identified generally as electrostatic discharges. The device includes a plurality of semiconductor elements, which are preferably bipolar transistors, coupled to the power rails and an input node or an output node of the circuit such that all types of electrostatic discharges can be diverted using the single device of the present invention. In the preferred embodiment of the invention the transistors have a common collector, their bases are open, and they are configured so that the emitter of one transistor is coupled to the high-potential power rail, the emitter of a second transistor is coupled to the low-potential power rail, and the emitter of a third transistor is coupled to the node to be protected. Various combinations of the breakdown characteristics of the several coupled transistors operate to divert all types of voltage spikes, including positive and negative spikes at the node, and positive and negative spikes between the power rails. The device of the present invention is smaller and faster than prior electrostatic discharge protection devices, with sufficient capacity to handle expected transient voltage levels.
摘要翻译：用于防止在电路的输入节点和输出节点以及高电位和低电位电源轨之间的电路损坏电压尖峰的装置。电压尖峰通常被称为静电放电。该器件包括多个半导体元件，其优选地是耦合到电源轨的双极晶体管，以及电路的输入节点或输出节点，使得可以使用本发明的单个器件转移所有类型的静电放电。在本发明的优选实施例中，晶体管具有公共集电极，它们的基极是开路的，并且它们被配置为使得一个晶体管的发射极耦合到高电位电源轨，第二晶体管的发射极耦合到低电位电源轨，第三晶体管的发射极耦合到待保护的节点。多个耦合晶体管的击穿特性的各种组合操作以转移所有类型的电压尖峰，包括节点处的正和负尖峰以及电源轨之间的正和负尖峰。本发明的装置比现有的静电放电保护装置更小和更快，具有足够的处理预期瞬态电压电平的能力。

3. 发明授权

US5223745A Power down Miller Killer circuit 失效
标题翻译：掉电铣刀电路
公开(公告)号：US5223745A
公开(公告)日：1993-06-29
申请号：US930471
申请日：1992-08-14
申请人： James R. Ohannes , Stephen W. Clukey , Ernest D. Haacke , Roy L. Yarbrough
发明人： James R. Ohannes , Stephen W. Clukey , Ernest D. Haacke , Roy L. Yarbrough
IPC分类号： H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/01 , H03K19/013 , H03K19/017 , H03K19/0175 , H03K19/08
CPC分类号： H03K19/0136 , H03K19/0016 , H03K19/01721
摘要： A circuit to be used with bistate and tristate output buffers as a means of diverting from the output pulldown transistor Miller Current arising while the output buffer is powered down. Its purpose is to avoid loading the common bus to which the output buffer is attached, in particular under the circumstances where other output buffers on the bus are causing transitions to occur and the buffer of interest has been powered down. In its preferred embodiment the invention utilizes a MOS transistor coupled between the output pulldown transistor and the lower potential power rail of the output buffer. This MOS transistor is controlled by another MOS transistor coupled to output V.sub.OUT of the buffers. This driver transistor is controlled by the high potential power rail of the buffer and so turns on the Miller Current Discharge Transistor only when the buffer is powered down. The invention also encompasses a discharge transistor coupled to the data input V.sub.IN to ensure that the Miller Current Discharge Transistor never pulls the of the output pulldown when the buffer is in its active low state.

4. 发明授权

US5204554A Partial isolation of power rails for output buffer circuits 失效
标题翻译：用于输出缓冲电路的电源轨的部分隔离
公开(公告)号：US5204554A
公开(公告)日：1993-04-20
申请号：US802747
申请日：1991-12-06
申请人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
发明人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
IPC分类号： H01L23/50 , H01L21/822 , H01L27/04 , H03K17/16 , H03K19/00 , H03K19/003
CPC分类号： H03K19/00346 , H03K17/16 , H01L2224/48091 , H01L2224/49175 , H01L2924/1305 , H01L2924/3011
摘要： An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V.sub.CCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V.sub.CCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V.sub.CCQ, V.sub.CCN) for reducing V.sub.CC droop in the relatively noisy supply rail (V.sub.CCN) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V.sub.OUT). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN). The coupling resistors (R5 and R5A) have low resistance values selected for partially coupling the supply and ground rails respectively, while maintaining partial isolation for protecting input dynamic threshold levels of quiet outputs. The first coupling resistor (R5) is coupled between supply rail bond pads (20,22), while the second coupling resistor (R5A) is coupled between ground rail bond pads (30,32). The power rail bond pads (20,22) (30,32) are coupled respectively to split leads (24,25) (34,35) of a split lead leadframe merging respectively to a common V.sub.CC pin (28) and a common GND pin (38).

5. 发明授权

US5184034A State-dependent discharge path circuit 失效
标题翻译：状态依赖放电路径电路
公开(公告)号：US5184034A
公开(公告)日：1993-02-02
申请号：US804906
申请日：1991-12-06
申请人： James R. Ohannes , Stephen W. Clukey , Ernest D. Haacke , Roy L. Yarbrough
发明人： James R. Ohannes , Stephen W. Clukey , Ernest D. Haacke , Roy L. Yarbrough
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/08 , H03K19/082 , H03K19/088 , H03K19/0944
CPC分类号： H03K19/0826 , H03K19/00307 , H03K19/09448
摘要： A circuit for use in connection with tristate output buffers in order to provide concurrently for fast discharge of the output pulldown transistor base and at the same time for building in protection against reverse breakdown in the pulldown transistor. The innovation consists of providing a two discharge paths to ground for the base of the output pullup transistor. A low-capacitance path is activated only while the output buffer is in its active mode. In the preferred embodiment of the invention, this low discharge path consists of two CMOS transistors in series, one of which is controlled by the enable signal input E of the buffer circuit and the other by the data signal input V.sub.IN of the buffer circuit. The other path to ground is available whenever the data signal input V.sub.IN is low, regardless of whether the buffer is in its active or inactive mode. This other path provides discharge protection for the base of the pullup transistor for the buffer in its inactive mode, and has incorporated into it reverse breakdown protection in the form of voltage drop devices such as forward-biased diodes.

6. 发明授权

US5521789A BICMOS electrostatic discharge protection circuit 失效
标题翻译： BICMOS静电放电保护电路
公开(公告)号：US5521789A
公开(公告)日：1996-05-28
申请号：US213661
申请日：1994-03-15
申请人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
发明人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An enhanced bipolar-transistor apparatus for protecting electronic devices from electrostatic discharge damage. The apparatus is built around a bipolar transistor coupled between a power rail and the circuit to be protected. The protection is based on the high-current-capacity path through the bipolar transistor which is opened up either by collector-to-emitter punch-through in the bipolar transistor or by the bipolar transistor going into normal conduction upon being turned on by a switch coupled to the base of the bipolar transistor. In the preferred embodiment the switch is a MOS transistor that is designed to undergo source-to-drain breakdown at a fixed threshold voltage, whereupon it activates the bipolar transistor which in turn discharges the overvoltage. In this way the advantages of the high-current-capacity bipolar transistor are obtained without the concern that fabrication vagaries will prevent the bipolar transistor from providing needed protection, such as is the situation where the punch-through phenomenon alone is relied on.
摘要翻译：一种用于保护电子器件免受静电放电损坏的增强型双极晶体管装置。该装置围绕耦合在电源轨和待保护电路之间的双极晶体管构成。该保护基于通过双极晶体管的大电流容量路径，其通过双极晶体管中的集电极到发射极穿通而被双极晶体管打开，或者通过由开关导通的双极晶体管进入正常导通耦合到双极晶体管的基极。在优选实施例中，开关是被设计成在固定阈值电压下经历源极到漏极击穿的MOS晶体管，于是它激活双极晶体管，该双极晶体管又导通过电压。以这种方式，可以获得大电流双极晶体管的优点，而不用担心制造变形会阻止双极晶体管提供所需的保护，例如仅依靠穿通现象的情况。

7. 发明授权

US5331224A I.sub.cct leakage current interrupter 失效
标题翻译： Icct漏电断流器
公开(公告)号：US5331224A
公开(公告)日：1994-07-19
申请号：US932354
申请日：1992-08-19
申请人： James R. Ohannes , Stephen W. Clukey
发明人： James R. Ohannes , Stephen W. Clukey
IPC分类号： H03K19/00 , H03K19/0944 , H03K17/16 , H03K19/094
CPC分类号： H03K19/0013 , H03K19/09448
摘要： An electronic switch to be used in BiCMOS circuitry when CMOS stages are controlled by logic output from (bipolar) TTL stages. Its purpose is to avoid the static leakage current I.sub.cct which can occur in a CMOS stage when the pulldown transistor is turned on while the pullup transistor is not completely turned off. This is a problem which arises when CMOS and TTL stages are coupled; the logic-high output from a TTL stage is sufficient in magnitude to turn on the CMOS pulldown transistor but not to turn off the CMOS pullup transistor. The present invention introduces an ancillary input to the subcircuit encompassing the CMOS input stage and also an ancillary output from one of the CMOS stages of the subcircuit (typically an output buffer) encompassing the TTL output stage. The ancillary output is chosen so as to provide a CMOS logic-high signal whenever the TTL stage is outputting a TTL logic-high signal. The ancillary input is connected to the control node of a switching transistor interposed between V.sub.cc and the CMOS input stage's pullup transistor. In this manner, the source of I.sub.cct is interrupted immediately after the CMOS stage is switched from pull-up mode to pull-down mode. The invention has particular applicability to latched transceivers, where the CMOS input stage is located in the latch circuit and the TTL in the tristate output buffer circuit.
摘要翻译：当CMOS级由（双极）TTL级的逻辑输出控制时，用于BiCMOS电路的电子开关。其目的是避免在下拉晶体管导通的同时在CMOS阶段发生的静态漏电流Icct，同时上拉晶体管未完全关断。这是CMOS和TTL级耦合时出现的问题; 来自TTL级的逻辑高输出的幅度足以打开CMOS下拉晶体管，但不能关闭CMOS上拉晶体管。本发明引入了包括CMOS输入级的分支电路的辅助输入，以及包含TTL输出级的子电路（通常是输出缓冲器）的CMOS级之一的辅助输出。选择辅助输出，以便每当TTL级输出TTL逻辑高电平信号时，提供CMOS逻辑高电平信号。辅助输入连接到插在Vcc和CMOS输入级上拉晶体管之间的开关晶体管的控制节点。以这种方式，在CMOS级从上拉模式切换到下拉模式之后，Icct的源被立即中断。本发明特别适用于锁存收发器，其中CMOS输入级位于锁存电路中，并且三态输出缓冲电路中的TTL位于锁存电路中。

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