专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140241380A1 MEDIA STREAM OVER PASS THROUGH MECHANISM 审中-公开
标题翻译：媒体流过机械通过
公开(公告)号：US20140241380A1
公开(公告)日：2014-08-28
申请号：US13992451
申请日：2011-11-17
申请人： Joseph A. Bennett , Guoging Li , Vallabhajosyula S. Somayazulu , George R. Hayek , Gideon Prat , Srikanth Kambhatla
发明人： Joseph A. Bennett , Guoging Li , Vallabhajosyula S. Somayazulu , George R. Hayek , Gideon Prat , Srikanth Kambhatla
IPC分类号： H04L29/06
CPC分类号： H04L69/22 , H04N21/2381 , H04N21/4381 , H04N21/643
摘要： A data packet or payload defined by a first format, is generated and is wrapped with headers as defined by a second format, and is processed through a pass through mechanism for transmission based on the second format. The processing includes adding or encapsulating the payload in the transmission data packet. When receiving the transmitted data packet, the headers may be parsed, and the payload processed.
摘要翻译：产生由第一格式定义的数据分组或有效负载，并且由第二格式定义的报头包裹，并且通过基于第二格式传输的传递机制进行处理。该处理包括将有效载荷添加或封装在传输数据包中。当接收到发送的数据分组时，可以解析报头，并且处理有效载荷。

2. 发明申请

US20150382035A1 METHOD AND APPARATUS FOR LOW JITTER CLOCK RECOVERY IN WIRELESS DISPLAY EXTENSIONS 有权
标题翻译：用于无线显示器扩展中低抖动时钟恢复的方法和装置
公开(公告)号：US20150382035A1
公开(公告)日：2015-12-31
申请号：US13996621
申请日：2011-12-21
申请人： Guoqing Li , Joseph A. Bennett , Gideon Prat , Solomon B. Trainin , Sang-Hee Lee , Vallabhajosyula Z. Somayazulu , George R. Hayek , Pat Brouillette , Dmitrii A. Loukianov
发明人： Guoqing Li , Joseph A. Bennett , Gideon Prat , Solomon B. Trainin , Sang-Hee Lee , Vallabhajosyula Z. Somayazulu , George R. Hayek , Pat Brouillette , Dmitrii A. Loukianov
IPC分类号： H04N21/242 , H04N21/61 , H04N21/43 , H04N21/236
CPC分类号： H04N21/242 , H04N21/23608 , H04N21/4305 , H04N21/6131
摘要： An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.
摘要翻译：提供了一种用于确定程序时钟参考（PCR）值有效性的方法，用于避免不准确的可变延迟引用（VDR）值，并且用于避免无线显示扩展的序列号和分组号之间的数据分组的不匹配。该方法包括确定生成具有可选PCR值，VDR值和有效性指示符的数据分组载体。该方法还可以涉及处理数据分组载波以确定数据分组载波是否具有任选的PCR值。该方法还可以包括至少部分地至少部分地导致至少部分地基于来自数据分组载体的确定的不存在可选PCR值来生成替代PCR值。

3. 发明授权

US09723342B2 Method and apparatus for low jitter clock recovery in wireless display extensions 有权
公开(公告)号：US09723342B2
公开(公告)日：2017-08-01
申请号：US13996621
申请日：2011-12-21
申请人： Guoqing Li , Joseph A. Bennett , Gideon Prat , Solomon B. Trainin , Sang-Hee Lee , Vallabhajosyula Z. Somayazulu , George R. Hayek , Pat Brouillette , Dmitrii A. Loukianov
发明人： Guoqing Li , Joseph A. Bennett , Gideon Prat , Solomon B. Trainin , Sang-Hee Lee , Vallabhajosyula Z. Somayazulu , George R. Hayek , Pat Brouillette , Dmitrii A. Loukianov
IPC分类号： H04N21/242 , H04N21/236 , H04N21/61 , H04N21/43
CPC分类号： H04N21/242 , H04N21/23608 , H04N21/4305 , H04N21/6131
摘要： An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

4. 发明授权

US06112284A Method and apparatus for latching data from a memory resource at a datapath unit 失效
标题翻译：用于在数据路径单元处从存储器资源锁存数据的方法和装置
公开(公告)号：US06112284A
公开(公告)日：2000-08-29
申请号：US367807
申请日：1994-12-30
申请人： George R. Hayek , Joe M. Nardone , Aniruddha Kundu , Kuljit S. Bains
发明人： George R. Hayek , Joe M. Nardone , Aniruddha Kundu , Kuljit S. Bains
IPC分类号： G11C7/10 , G06F13/16
CPC分类号： G11C7/1018 , G11C7/1024
摘要： A memory controller having a data strobe that tracks the column access strobe signal in a computer system having Extended Data Out (EDO) DRAMs. The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column access strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to said data strobe signal, at approximately the center of the valid window.
摘要翻译：具有在具有扩展数据输出（EDO）DRAM的计算机系统中跟踪列存取选通信号的数据选通器的存储器控制器。数据选通信号以预定的延迟跟随列存取选通信号，因此列存取选通信号中的任何偏移固有地包括在数据选通信号内。结果，可以在有效窗口的大约中心处响应于所述数据选通信号来锁存数据。

5. 发明申请

US20120079295A1 TECHNIQUES TO TRANSMIT COMMANDS TO A TARGET DEVICE 有权
标题翻译：将命令发送到目标设备的技术
公开(公告)号：US20120079295A1
公开(公告)日：2012-03-29
申请号：US12890217
申请日：2010-09-24
申请人： George R. Hayek , Todd M. Witter , Seh W. Kwa , Maximino Vasquez
发明人： George R. Hayek , Todd M. Witter , Seh W. Kwa , Maximino Vasquez
IPC分类号： G06F1/32
CPC分类号： G06F1/3265 , G06F1/266 , G06F1/3218 , G06F1/3287 , G06F1/3293 , G06F3/0659 , G09G5/006 , G09G5/395 , G09G2330/021 , G09G2360/18 , G09G2370/04 , G09G2370/10 , G09G2370/14 , Y02D10/153 , Y02D10/171 , Y02D50/20
摘要： Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.
摘要翻译：描述技术来将命令传送到显示设备。这些命令可以在辅助数据包的头字节字段中传输。这些命令可用于使目标设备捕获帧，进入或退出自刷新模式或减少连接的电力使用。此外，退出主链路待机模式的请求可能导致目标进入训练模式而不显式命令退出主链路待机模式。

6. 发明授权

US5911051A High-throughput interconnect allowing bus transactions based on partial access requests 失效
标题翻译：高吞吐量互连允许基于部分访问请求的总线事务
公开(公告)号：US5911051A
公开(公告)日：1999-06-08
申请号：US721686
申请日：1996-09-27
申请人： David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case , Kim A. Meinerth , Brian K. Langendorf
发明人： David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case , Kim A. Meinerth , Brian K. Langendorf
IPC分类号： G06F13/16 , G06F13/14
CPC分类号： G06F13/1631 , G06F13/161 , G06F13/1615
摘要： A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.
摘要翻译：提供了高吞吐量的存储器访问接口。该接口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。该接口允许以这样的方式执行存储器访问请求，使得只有访问请求的一部分需要被发送到目标设备以用于某些总线事务。每个访问请求包括命令位，地址位和长度位。在发起设备中，每个访问请求被分成三个段，它们存储在起始设备和目标设备中的单独的寄存器中。目标设备只需要包含最低位地址位和长度位的段来启动总线事务。因此，如果其他两个段中的任何一个从先前的访问请求起没有改变，则这样的段或段不被发送到目标。如果这些片段或片段自从先前的访问请求以来已经改变，那么它们被提供给目标，仅用于更新目标中的状态。访问请求可以可选地在与用于响应于访问请求传输数据的端口的单独端口上提供给目标。

7. 发明授权

US06317803B1 High-throughput interconnect having pipelined and non-pipelined bus transaction modes 失效
标题翻译：具有流水线和非流水线总线事务模式的高吞吐量互连
公开(公告)号：US06317803B1
公开(公告)日：2001-11-13
申请号：US08721893
申请日：1996-09-27
申请人： Norman J. Rasmussen , Gary A. Solomon , David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case
发明人： Norman J. Rasmussen , Gary A. Solomon , David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case
IPC分类号： G06F1300
CPC分类号： G06F13/1615 , G06F13/161 , G06F13/1631
摘要： A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.
摘要翻译：提供了高吞吐量的存储器访问端口。该端口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。该端口允许内存读取和写入请求流水线，以隐藏内存访问延迟的影响。特别地，端口允许以非流水线模式（例如由PCI提供）或以流水线模式执行总线事务。在流水线模式中，允许在第一存储器访问请求和其对应的数据传送之间插入一个或多个附加存储器访问请求。相比之下，在非流水线模式下，不能在第一存储器访问请求和其对应的数据传输之间插入附加存储器访问请求。

8. 发明授权

US5918025A Method and apparatus for converting a five wire arbitration/buffer management protocol into a two wire protocol 失效
标题翻译：将五线仲裁/缓冲管理协议转换为双线协议的方法和装置
公开(公告)号：US5918025A
公开(公告)日：1999-06-29
申请号：US775807
申请日：1996-12-31
申请人： George R. Hayek , Brian Langendorf , Jasmin Ajanovic , Rajeev K. Prasad
发明人： George R. Hayek , Brian Langendorf , Jasmin Ajanovic , Rajeev K. Prasad
IPC分类号： G06F13/362 , G06F13/40 , G06F13/00
CPC分类号： G06F13/362 , G06F13/4031
摘要： A method for converting signals from one arbitration and management protocol to another. The conversion is performed by at least three state machines. The conversion circuit converts a set of signals on the first bus to a bus request signal on the second bus. The conversion circuit also converts a signal from the second bus and a set of signals on the first bus to bus grant and memory acknowledge signals on the first bus.
摘要翻译：一种将信号从一个仲裁和管理协议转换到另一个的方法。该转换由至少三台状态机执行。转换电路将第一总线上的一组信号转换为第二总线上的总线请求信号。转换电路还将来自第二总线的信号和第一总线上的一组信号转换为第一总线上的总线授权和存储器确认信号。

9. 发明授权

US5740385A Low load host/PCI bus bridge 失效
标题翻译：低负载主机/ PCI总线桥
公开(公告)号：US5740385A
公开(公告)日：1998-04-14
申请号：US358359
申请日：1994-12-19
申请人： George R. Hayek , Brian K. Langendorf , Aniruddha Kundu , Kuljit S. Bains , Gary A. Solomon
发明人： George R. Hayek , Brian K. Langendorf , Aniruddha Kundu , Kuljit S. Bains , Gary A. Solomon
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.
摘要翻译：用于将主机总线耦合到外围组件互连（PCI）总线的桥。当使用数据路径从主机总线传输数据时，控制器用于从主机总线传输地址。然后将地址和数据通过耦合到PCI总线的一组信号线传送到PCI总线，使得每个信号线传送地址的至少一部分以及数据的至少一部分。

10. 发明授权

US5978952A Time-distributed ECC scrubbing to correct memory errors 失效
标题翻译：时间分配的ECC擦除来纠正内存错误
公开(公告)号：US5978952A
公开(公告)日：1999-11-02
申请号：US777252
申请日：1996-12-31
申请人： George R. Hayek , Radhakrishnan Venkataraman , Jasmin Ajanovic
发明人： George R. Hayek , Radhakrishnan Venkataraman , Jasmin Ajanovic
IPC分类号： G06F11/10 , G11C11/403 , G06F11/00 , G11C29/00
CPC分类号： G06F11/106 , G11C29/52 , G06F11/1028 , G06F11/1052 , G11C2029/0409
摘要： Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that contains the correctable error is latched for later used by an interrupt-driven firmware memory-error scrub routine. This routine reads and rewrites each word within the indicated memory section--the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors. System management interrupts and firmware may be used to implement the memory-error scrub routine, which makes it independent of and transparent to the various operating systems that may be run on the computer system.
摘要翻译：误差校正电路尝试检测并校正计算机系统内随机存取存储器（RAM）内的错误字。 RAM错误被擦除或校正回内存，而不会延迟内存访问周期。相反，包含可纠正错误的部分或一行RAM的地址被锁存，供以后由中断驱动的固件内存错误擦除例程使用。该例程读取并重写所指示的存储器部分中的每个单词 - 读取该错误的单词，在读取时在其上进行正确校正，然后将其重写回存储器。如果存储器部分的大小超过预定阈值，则将该部分的读取和重写的处理分成使用延迟的中断机制在时间上分布的更小的子进程。每个内存清理子进程的持续时间保持足够短，以免在擦除RAM内存错误的内务任务时计算机系统的响应时间不会受损。可以使用系统管理中断和固件来实现内存错误擦除例程，这使其独立于可能在计算机系统上运行的各种操作系统的透明度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式