专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5911051A High-throughput interconnect allowing bus transactions based on partial access requests 失效
标题翻译：高吞吐量互连允许基于部分访问请求的总线事务
公开(公告)号：US5911051A
公开(公告)日：1999-06-08
申请号：US721686
申请日：1996-09-27
申请人： David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case , Kim A. Meinerth , Brian K. Langendorf
发明人： David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case , Kim A. Meinerth , Brian K. Langendorf
IPC分类号： G06F13/16 , G06F13/14
CPC分类号： G06F13/1631 , G06F13/161 , G06F13/1615
摘要： A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.
摘要翻译：提供了高吞吐量的存储器访问接口。该接口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。该接口允许以这样的方式执行存储器访问请求，使得只有访问请求的一部分需要被发送到目标设备以用于某些总线事务。每个访问请求包括命令位，地址位和长度位。在发起设备中，每个访问请求被分成三个段，它们存储在起始设备和目标设备中的单独的寄存器中。目标设备只需要包含最低位地址位和长度位的段来启动总线事务。因此，如果其他两个段中的任何一个从先前的访问请求起没有改变，则这样的段或段不被发送到目标。如果这些片段或片段自从先前的访问请求以来已经改变，那么它们被提供给目标，仅用于更新目标中的状态。访问请求可以可选地在与用于响应于访问请求传输数据的端口的单独端口上提供给目标。

2. 发明授权

US6097402A System and method for placement of operands in system memory 失效
标题翻译：在系统内存中放置操作数的系统和方法
公开(公告)号：US6097402A
公开(公告)日：2000-08-01
申请号：US21192
申请日：1998-02-10
申请人： Colyn Case , Brian K. Langendorf , George R. Hayek , Kim A. Meinerth
发明人： Colyn Case , Brian K. Langendorf , George R. Hayek , Kim A. Meinerth
IPC分类号： G06F3/14 , G06F15/167
CPC分类号： G06F3/14
摘要： A method and system for enhancing graphics processing through selected placement of at least one graphics operand in main memory. The system includes a graphics controller in communication with system memory through a dedicated graphics bus such as an Accelerated Graphics Port (AGP) bus. This allows texture maps, alpha blending data and other graphics information to be contained in system memory without degradation of system performance.
摘要翻译：一种用于通过在主存储器中选择放置至少一个图形操作数来增强图形处理的方法和系统。该系统包括通过诸如加速图形端口（AGP）总线的专用图形总线与系统存储器通信的图形控制器。这允许纹理贴图，alpha混合数据和其他图形信息包含在系统存储器中，而不会降低系统性能。

3. 发明授权

US5640519A Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme 失效
标题翻译：一种用于改善代理在循环仲裁方案下经历的延迟的方法和装置
公开(公告)号：US5640519A
公开(公告)日：1997-06-17
申请号：US528914
申请日：1995-09-15
申请人： Brian K. Langendorf , James M. Dodd , George R. Hayek
发明人： Brian K. Langendorf , James M. Dodd , George R. Hayek
IPC分类号： G06F13/364 , G06F13/36 , G06F13/362
CPC分类号： G06F13/364
摘要： An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal. This control signal signals the mapping circuit to disable at least one of the plurality of request signals upon detecting that the control signal is associated with the first I/O port or the second I/O port.
摘要翻译：仲裁电路，其由包括等待时间敏感代理的第一多个代理控制资源的仲裁。仲裁电路包括映射电路和仲裁器。映射电路耦合到第一多个代理，以便从等待时间敏感代理接收资源请求信号，然后产生与资源请求信号相同的多个请求信号。这些请求信号被输入到仲裁器的至少第一和第二I / O端口中。耦合到映射电路的仲裁器包括每个对应于一个I / O端口的第二多个I / O端口和第二多个控制端口。仲裁器被配置为仲裁输入到包括多个请求信号的第二多个I / O端口的请求信号，以监视上一次激活的I / O端口，并且停用与I / O端口相关联的控制端口，从而产生控制信号。该控制信号在检测到控制信号与第一I / O端口或第二I / O端口相关联时，通知该映射电路来禁用多个请求信号中的至少一个。

4. 发明授权

US5603010A Performing speculative system memory reads prior to decoding device code 失效
标题翻译：在解码设备代码之前执行推测系统存储器读取
公开(公告)号：US5603010A
公开(公告)日：1997-02-11
申请号：US580323
申请日：1995-12-28
申请人： James M. Dodd , Richard Malinowski , Brian K. Langendorf , George R. Hayek
发明人： James M. Dodd , Richard Malinowski , Brian K. Langendorf , George R. Hayek
IPC分类号： G06F12/04 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4239
摘要： A method of improving computer system performance during memory reads. Prior art computer systems experience a considerable time penalty during microprocessor reads from system memory. This time penalty is mitigated by the method of the present invention, wherein data is speculatively retrieved from system memory upon receipt of a microprocessor read request. A microprocessor initiates a read request which is decoded by a memory controller. Before the decoding has completed, the memory controller speculatively begins to retrieve data from the system memory device. Thus if the decode step determines that the requested data is in system memory, the time required to retrieve the data is decreased.
摘要翻译：一种在存储器读取期间提高计算机系统性能的方法。现有技术的计算机系统在从系统存储器的微处理器读取期间经历相当多的时间损失。通过本发明的方法减轻了该时间的损失，其中在接收到微处理器读取请求时，从系统存储器中推测性地检索数据。微处理器启动由存储器控制器解码的读请求。在解码完成之前，存储器控制器推测开始从系统存储器件中检索数据。因此，如果解码步骤确定所请求的数据在系统存储器中，则检索数据所需的时间减少。

5. 发明授权

US5740385A Low load host/PCI bus bridge 失效
标题翻译：低负载主机/ PCI总线桥
公开(公告)号：US5740385A
公开(公告)日：1998-04-14
申请号：US358359
申请日：1994-12-19
申请人： George R. Hayek , Brian K. Langendorf , Aniruddha Kundu , Kuljit S. Bains , Gary A. Solomon
发明人： George R. Hayek , Brian K. Langendorf , Aniruddha Kundu , Kuljit S. Bains , Gary A. Solomon
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.
摘要翻译：用于将主机总线耦合到外围组件互连（PCI）总线的桥。当使用数据路径从主机总线传输数据时，控制器用于从主机总线传输地址。然后将地址和数据通过耦合到PCI总线的一组信号线传送到PCI总线，使得每个信号线传送地址的至少一部分以及数据的至少一部分。

6. 发明授权

US06760031B1 Upgrading an integrated graphics subsystem 有权
标题翻译：升级集成图形子系统
公开(公告)号：US06760031B1
公开(公告)日：2004-07-06
申请号：US09476658
申请日：1999-12-31
申请人： Brian K. Langendorf , Thomas A. Piazza
发明人： Brian K. Langendorf , Thomas A. Piazza
IPC分类号： G06F1516
CPC分类号： G06F3/14 , G06F3/1438 , G09G5/363 , G09G5/393 , G09G2352/00 , G09G2360/06
摘要： Apparatus and methods are provided for allowing two graphics controllers to cooperate on a single screen and for modifying the AGP protocol to provide symmetric capabilities for both AGP targets and AGP masters. According to one embodiment of the present invention two graphics controllers may cooperate as one virtual graphics controller. A first graphics controller renders a first subset of pixels of a display to a local memory of the first graphics controller. A second graphics controller renders a second subset of pixels of the display to a local memory of the second graphics controller. Then, after both the first graphics controller and the second graphics controller have completed their respective rendering, merging the content of the local memory of the first graphics controller and the content of the local memory of the second graphics controller.
摘要翻译：提供了装置和方法，用于允许两个图形控制器在单个屏幕上协作并且用于修改AGP协议以为AGP目标和AGP主机提供对称能力。根据本发明的一个实施例，两个图形控制器可以协作为一个虚拟图形控制器。第一图形控制器将显示器的像素的第一子集渲染到第一图形控制器的本地存储器。第二图形控制器将显示器的像素的第二子集呈现给第二图形控制器的本地存储器。然后，在第一图形控制器和第二图形控制器都已经完成它们各自的渲染之后，合并第一图形控制器的本地存储器的内容和第二图形控制器的本地存储器的内容。

7. 发明授权

US6092158A Method and apparatus for arbitrating between command streams 失效
标题翻译：命令流之间进行仲裁的方法和装置
公开(公告)号：US6092158A
公开(公告)日：2000-07-18
申请号：US874414
申请日：1997-06-13
申请人： David J. Harriman , Brian K. Langendorf , Jasmin Ajanovic
发明人： David J. Harriman , Brian K. Langendorf , Jasmin Ajanovic
IPC分类号： G06F13/16 , G06F12/00 , G06F13/00
CPC分类号： G06F13/1642
摘要： A method and apparatus for arbitrating between command streams. The method unblocks high priority commands which are blocked and then selects any remaining high priority commands. Normal priority commands are selected after the high priority commands. A memory controller described includes a command queue block having a plurality of command queues, each being coupled to receive a different type of command. The memory controller also includes arbitration logic which, among other things, selects high priority read commands before high priority write commands. Memory interface logic generates memory accesses performing commands selected by the arbitration logic.
摘要翻译：一种用于在命令流之间进行仲裁的方法和装置。该方法解除阻塞的高优先级命令，然后选择剩余的高优先级命令。在优先级高的命令之后选择正常优先级命令。所描述的存储器控制器包括具有多个命令队列的命令队列块，每个命令队列被耦合以接收不同类型的命令。存储器控制器还包括仲裁逻辑，其中除了别的以外，在高优先级写入命令之前选择高优先级的读取命令。存储器接口逻辑产生执行由仲裁逻辑选择的命令的存储器访问。

8. 发明授权

US07054987B1 Apparatus, system, and method for avoiding data writes that stall transactions in a bus interface 有权
标题翻译：用于避免在总线接口中停止事务的数据写入的装置，系统和方法
公开(公告)号：US07054987B1
公开(公告)日：2006-05-30
申请号：US10741069
申请日：2003-12-19
申请人： David G. Reed , Brian K. Langendorf , Brad W. Simeral , Anand Srinivasan
发明人： David G. Reed , Brian K. Langendorf , Brad W. Simeral , Anand Srinivasan
IPC分类号： G06F13/00 , G06F13/14 , G06F13/38 , G06F11/00 , G06F12/00
CPC分类号： G06F13/16
摘要： A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource associated with servicing transaction requests to the targets, such as a posted write buffer. If a transaction request would fill the resource beyond a current remaining capacity of the resource such that the execution of other pipelined transactions would become stalled, the bus interface generates a retry response so that the request is retried at a later time, permitting other transactions to proceed while the resource drains.
摘要翻译：总线接口单元适于接收至少两个不同目标的交易请求。总线接口单元监视与针对目标的事务请求的服务相关联的资源的容量，例如已发布的写入缓冲器。如果事务请求将超过资源的当前剩余容量填充资源，使得其他流水线事务的执行将变得停滞，则总线接口产生重试响应，以便稍后重试该请求，允许其他事务在资源耗尽时继续进行。

9. 发明授权

US06823418B2 Virtual PCI device apparatus and method 有权
标题翻译：虚拟PCI设备及方法
公开(公告)号：US06823418B2
公开(公告)日：2004-11-23
申请号：US09896395
申请日：2001-06-29
申请人： Brian K. Langendorf , Varghese George
发明人： Brian K. Langendorf , Varghese George
IPC分类号： G06F1300
CPC分类号： G06F13/105
摘要： Virtual PCI bus appears from the perspective of a computer program to be a part of a physical hierarchical PCI bus structure residing behind a host-to-PCI bridge. Devices that are physically located on the host bus side of the host-to-PCI bridge may appear as virtual devices residing on the virtual PCI bus allowing the physical devices to participate in device independent initialization and system resource allocation generally available only to PCI compliant devices. Processor initiated host bus cycles targeted to the virtual PCI device may be intercepted and redirected to the physical device.
摘要翻译：虚拟PCI总线从计算机程序的角度出现，成为位于主机到PCI桥后面的物理分层PCI总线结构的一部分。物理上位于主机到PCI桥接器主机总线侧的设备可以显示为位于虚拟PCI总线上的虚拟设备，允许物理设备参与独立于设备的初始化和通常仅适用于PCI兼容设备的系统资源分配。针对虚拟PCI设备的处理器发起的主机总线周期可能会被拦截并重定向到物理设备。

10. 发明授权

US06313766B1 Method and apparatus for accelerating software decode of variable length encoded information 失效
标题翻译：用于加速可变长度编码信息的软件解码的方法和装置
公开(公告)号：US06313766B1
公开(公告)日：2001-11-06
申请号：US09109008
申请日：1998-07-01
申请人： Brian K. Langendorf , Brian Tucker
发明人： Brian K. Langendorf , Brian Tucker
IPC分类号： G06F1500
CPC分类号： H04N19/91 , H04N19/61
摘要： A method and apparatus to accelerate variable length decode is disclosed. The system includes a logic device to receive a bit stream of variable length encoded information. The logic device outputs a fixed length value corresponding to a variable length code received as part of the bit stream of the variable length encoded information. The system also includes a processor to receive the fixed length value. The processor to performs a write of a coefficient to a system memory device, the coefficient corresponding to the fixed length value received from the logic device.
摘要翻译：公开了一种用于加速可变长度解码的方法和装置。该系统包括用于接收可变长度编码信息的比特流的逻辑设备。逻辑装置输出与作为可变长度编码信息的比特流的一部分接收的可变长度码对应的固定长度值。该系统还包括一个接收固定长度值的处理器。所述处理器对系统存储器件执行系数的写入，所述系数对应于从所述逻辑器件接收的所述固定长度值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式