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1. 发明授权

US06300205B1 Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions 有权
标题翻译：制造具有自对准有源，轻掺杂漏极和卤区的半导体器件的方法
公开(公告)号：US06300205B1
公开(公告)日：2001-10-09
申请号：US09193262
申请日：1998-11-18
申请人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
发明人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.
摘要翻译：制造半导体器件的一种方法包括在衬底上形成栅电极并在栅电极的侧壁上形成间隔物。然后，使用第一掺杂剂材料，在衬底中形成有源区并与间隔物相邻，但与栅电极间隔开。使用不同于第一掺杂剂材料的导电类型的第二掺杂剂材料，在间隔物下方的衬底中形成晕圈区域并与有源区相邻。可以通过相对于衬底的表面以相对小于90°的角度将第二掺杂剂区域注入到衬底中来形成晕圈区域。然后去除间隔物的一部分，并且使用与第一掺杂剂材料相同的导电类型的第三掺杂剂材料，在邻近有源区和栅电极的衬底中形成轻掺杂区域，并且比晕区浅。

2. 发明授权

US6114211A Semiconductor device with vertical halo region and methods of manufacture 有权
标题翻译：具有垂直卤区的半导体器件及其制造方法
公开(公告)号：US6114211A
公开(公告)日：2000-09-05
申请号：US195336
申请日：1998-11-18
申请人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
发明人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
IPC分类号： H01L21/336 , H01L29/10
CPC分类号： H01L29/66492 , H01L29/1083 , H01L29/6653 , H01L29/6659
摘要： One method of forming a semiconductor device includes forming a gate electrode on a substrate and then forming a spacer adjacent to a sidewall of the gate electrode. An active region is formed in the substrate adjacent to the spacer and spaced apart from the gate electrode using a first dopant material of a first conductivity type. A protecting layer is formed over the active region and adjacent to the spacer. At least a portion of the spacer is then removed to form an opening between the protecting layer and the gate electrode. In some instances, the spacer may be formed by independent deposition of two different materials (e.g., silicon nitride and silicon dioxide), one of which can be selectively removed with respect to the other. A lightly-doped region is formed in the substrate adjacent to the gate electrode using a second dopant material of the first conductivity type. This lightly-doped region may be formed, for example, prior to formation of the spacer, between the formation of two portions of the spacer, or after removing at least a portion of the spacer. A halo region is formed through the opening resulting from removing a portion of the spacer. The halo region is deeper in the substrate than the lightly-doped region and is adjacent to the active region. The halo region is formed using a third dopant material of a conductivity type different than the first conductivity type.
摘要翻译：形成半导体器件的一种方法包括在衬底上形成栅电极，然后形成与栅电极的侧壁相邻的间隔物。使用第一导电类型的第一掺杂剂材料，在与衬垫相邻的衬底中形成有源区，并与栅电极间隔开。保护层形成在有源区上并与隔片相邻。然后去除间隔物的至少一部分以在保护层和栅电极之间形成开口。在一些情况下，可以通过独立沉积两种不同材料（例如，氮化硅和二氧化硅）来形成隔离物，其中一种可以相对于另一种材料选择性地去除。使用第一导电类型的第二掺杂剂材料在与栅电极相邻的衬底中形成轻掺杂区域。该轻掺杂区域例如可以在形成间隔物之前，在间隔物的两个部分的形成之间或在移除间隔物的至少一部分之后形成。通过从隔离物的一部分去除而形成的晕圈形成。卤素区域在衬底中比轻掺杂区域更深，并且与有源区域相邻。卤素区域是使用不同于第一导电类型的导电类型的第三掺杂剂材料形成的。

3. 发明授权

US6074906A Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers 失效
标题翻译：具有使用多个间隔物形成的源/漏区的互补金属氧化物半导体器件
公开(公告)号：US6074906A
公开(公告)日：2000-06-13
申请号：US958534
申请日：1997-10-27
申请人： Jon Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864
摘要： A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively. A third n-type dopant is selectively implanted into the NMOS active region using the second NMOS spacer as a mask to form a third n-doped region deeper than the second n-doped region in the NMOS active region. A second p-type dopant is selectively implanted into the PMOS active region using the second PMOS spacer as a mask to form a second p-doped region in the PMOS active region deeper than the first p-doped region.
摘要翻译：具有使用多个间隔物形成的NMOS源极/漏极区域的CMOS半导体器件具有至少一个NMOS区域和至少一个PMOS区域。第一n型掺杂剂被选择性地注入到与NMOS栅电极相邻的衬底的NMOS有源区中，以在NMOS有源区中形成第一n掺杂区。第一NMOS间隔物形成在NMOS栅电极的侧壁和PMOS栅电极的侧壁上的第一PMOS间隔物上。使用第一NMOS间隔物作为掩模，将第二n型掺杂剂选择性地注入NMOS有源区。使用第一PMOS间隔物作为掩模将p型掺杂剂选择性地注入PMOS有源区，以在PMOS有源区中形成第一p掺杂区。分别与第一NMOS间隔物和第一PMOS间隔物相邻地形成第二NMOS间隔物和第二PMOS间隔物。使用第二NMOS间隔物作为掩模，将第三n型掺杂剂选择性地注入NMOS有源区，以形成比NMOS有源区中的第二n掺杂区更深的第三n掺杂区。使用第二PMOS间隔物作为掩模将第二p型掺杂剂选择性地注入到PMOS有源区中，以在PMOS有源区中形成比第一p掺杂区更深的第二p掺杂区。

4. 发明授权

US06417539B2 High density memory cell assembly and methods 有权
标题翻译：高密度存储单元组装及方法
公开(公告)号：US06417539B2
公开(公告)日：2002-07-09
申请号：US09128864
申请日：1998-08-04
申请人： Mark I. Gardner , Derick J. Wristers , Jon Cheek
发明人： Mark I. Gardner , Derick J. Wristers , Jon Cheek
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode form the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode. The memory cell assembly can be made by, first, forming a first electrode over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.
摘要翻译：存储单元组件包括衬底，第一电极和第二电极层。第一电极设置在衬底上，并且第二电极层设置在第一电极上。第二电极层包括两个或更多个第二电极。电介质材料将第一电极与第二电极分开，并分离第二电极。每个第二电极形成与第一电极相关联的单个存储单元。存储单元组件可以通过首先在衬底上形成第一电极来制造。在第一电极上形成第二电极层。第二电极层包括两个或更多个第二电极。在第一电极和第二电极之间以及第二电极之间形成电介质材料。

5. 发明授权

US5935766A Method of forming a conductive plug in an interlevel dielectric 失效
标题翻译：在层间电介质中形成导电塞的方法
公开(公告)号：US5935766A
公开(公告)日：1999-08-10
申请号：US908487
申请日：1997-08-07
申请人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
发明人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/768 , H01L23/522 , G03F7/00 , H01L21/02
CPC分类号： H01L23/5226 , H01L21/76838 , H01L2924/0002
摘要： A method of forming a conductive plug in an interlevel dielectric includes forming a lower dielectric layer over a semiconductor substrate. A first etch mask is formed over the lower dielectric layer and is patterned using a reticle. A first etch is applied through an opening in the first etch mask to form an opening in the lower dielectric layer. A lower conductor is formed in the opening in the lower dielectric layer. A conducting layer is formed over the lower dielectric layer and the lower conductor. A second etch mask is formed over the conducting layer and is patterned using the reticle. A second etch is applied through an opening in the second etch mask to form a contact pad from an unetched portion of the conducting layer. An upper dielectric layer is formed over the lower dielectric layer and the contact pad. A third etch mask is formed over the upper dielectric layer and is patterned using the reticle. A third etch is applied through an opening in the third etch mask to form an opening in the upper dielectric layer. An upper conductor is formed in the opening in the upper dielectric layer. As a result, the conductive plug includes the upper and lower conductors and the contact pad, and the interlevel dielectric includes the upper and lower dielectric layers.
摘要翻译：在层间电介质中形成导电插塞的方法包括在半导体衬底上形成下介电层。在下介电层上形成第一蚀刻掩模，并使用掩模版进行图案化。通过第一蚀刻掩模中的开口施加第一蚀刻，以在下介电层中形成开口。下导体形成在下电介质层的开口中。在下介电层和下导体上形成导电层。在导电层上形成第二蚀刻掩模，并使用掩模版进行图案化。通过第二蚀刻掩模中的开口施加第二蚀刻，以从导电层的未蚀刻部分形成接触焊盘。在下电介质层和接触焊盘上形成上介电层。在上电介质层上形成第三蚀刻掩模，并使用掩模版进行图案化。通过第三蚀刻掩模中的开口施加第三蚀刻，以在上介电层中形成开口。上导体形成在上电介质层的开口中。结果，导电插塞包括上导体和下导体和接触垫，并且层间电介质包括上和下介电层。

6. 发明授权

US06242330B1 Process for breaking silicide stringers extending between silicide areas of different active regions 失效
标题翻译：用于破坏在不同活性区域的硅化物区域之间延伸的硅化物桁条的方法
公开(公告)号：US06242330B1
公开(公告)日：2001-06-05
申请号：US08994200
申请日：1997-12-19
申请人： Jon Cheek , Derick J. Wristers , Fred Hause
发明人： Jon Cheek , Derick J. Wristers , Fred Hause
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518
摘要： A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over the two adjacent silicon active regions. The metal layer is then reacted with the silicon active regions to form a metal silicide on each silicon active region. This silicide reaction also forms silicide stringers extending from each silicon active region. Finally, at least part of each silicide stringer is removed. During the formation of the silicide stringers at least one silicide stringer may be formed which bridges the metal silicide over one of the silicon regions and the metal silicide over the other silicon region. In such circumstances, the removal process may, for example, break the silicide stringer and electrically decouple the two silicon regions. The two silicon active regions may, for example, be a gate electrode and an adjacet source/drain region. As another example, the two adjacent active regions may be two nearby polysilicon lines.
摘要翻译：提供了一种用于在半导体器件上破坏在不同有源区的硅化物区之间延伸的硅化物桁条的工艺。与示例性制造工艺一致，在衬底上形成两个相邻的硅有源区，并且在两个相邻的硅有源区上形成金属层。然后金属层与硅有源区反应，以在每个硅有源区上形成金属硅化物。这种硅化物反应也形成从每个硅活性区延伸的硅化物桁条。最后，每个硅化物纵梁的至少部分被去除。在硅化物桁条的形成期间，可以形成至少一个硅化物桁条，其将金属硅化物跨过其中一个硅区域和金属硅化物超过另一个硅区域。在这种情况下，移除过程可能会例如破坏硅化物纵梁并使两个硅区域电耦合。两个硅有源区可以例如是栅电极和辅助源/漏区。作为另一示例，两个相邻的有源区可以是两个附近的多晶硅线。

7. 发明授权

US5976925A Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate electrode 失效
标题翻译：制造具有非对称掺杂有源区和栅电极的半导体器件的工艺
公开(公告)号：US5976925A
公开(公告)日：1999-11-02
申请号：US980636
申请日：1997-12-01
申请人： Jon Cheek , Derick J. Wristers , James F. Buller
发明人： Jon Cheek , Derick J. Wristers , James F. Buller
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/6659 , H01L21/823418 , H01L29/665
摘要： A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a first dopant to form a doped polysilicon layer. Portions of the doped polysilicon layer are then removed to form at least one gate electrode. Active regions of the substrate adjacent the gate electrode are implanted with a second dopant to form source/drain regions in the substrate. In this manner, the implant used to form the source/drain regions may be decoupled from the implant used to form the gate electrode. This, for example, allows for shallower source/drain regions to be formed without the formation of the depletion layer in the gate electrode.
摘要翻译：提供具有非对称掺杂的栅电极和有源区的半导体器件和制造这种器件的工艺。根据本发明的一个实施例，在衬底上形成多晶硅层。然后用第一掺杂剂注入多晶硅层以形成掺杂多晶硅层。然后去除掺杂多晶硅层的部分以形成至少一个栅电极。与栅电极相邻的衬底的有源区注入第二掺杂剂以在衬底中形成源极/漏极区。以这种方式，用于形成源极/漏极区域的植入物可以与用于形成栅电极的植入物去耦合。例如，这允许形成更浅的源/漏区，而不在栅电极中形成耗尽层。

8. 发明授权

US5970311A Method and structure for optimizing the performance of a semiconductor device having dense transistors 失效
标题翻译：用于优化具有致密晶体管的半导体器件的性能的方法和结构
公开(公告)号：US5970311A
公开(公告)日：1999-10-19
申请号：US961980
申请日：1997-10-31
申请人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
发明人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/66 , H01L23/544 , H01L21/00 , G01R31/26
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/0002
摘要： A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate electrode formed at a design width and at a first line spacing similar to the line spacing of a dense transistor. One or more electrical properties the transistor of the first test structure is measured. A second test structure is formed on a second substrate portion. The second test structure includes a transistor having a gate electrode formed at the same design width as the transistor of the first test structure and at a second line spacing greater than the first line spacing. One or more electrical properties of the transistor of the second test structure are measured. Using the measured one or more electrical properties, one or more relationships are developed between the measured one or more electrical properties and the transistors at the first line spacing and the second line spacing.
摘要翻译：一种用于优化具有致密晶体管的半导体器件的性能的方法和结构。与本发明一致的方法包括在第一衬底部分上形成第一测试结构。第一测试结构包括晶体管，其晶体管具有以类似于致密晶体管的线间距的设计宽度和第一行间距形成的栅电极。测量第一测试结构的晶体管的一个或多个电特性。在第二基板部分上形成第二测试结构。第二测试结构包括晶体管，其晶体管具有与第一测试结构的晶体管相同的设计宽度并且在大于第一线间距的第二线间距处形成栅电极。测量第二测试结构的晶体管的一个或多个电特性。使用所测量的一个或多个电性能，在所测量的一个或多个电性能和在第一线间距和第二线间距处的晶体管之间形成一个或多个关系。

9. 发明申请

US20070218618A1 INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路的中间层电介质
公开(公告)号：US20070218618A1
公开(公告)日：2007-09-20
申请号：US11754728
申请日：2007-05-29
申请人： James Burnett , Jon Cheek
发明人： James Burnett , Jon Cheek
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823807 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L27/1203 , H01L29/7843 , Y10S257/903
摘要： An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.
摘要翻译：具有逻辑和静态随机存取存储器（SRAM）阵列的集成电路通过针对SRAM阵列处理不同于逻辑的层间电介质（ILD）而提高了性能。 N沟道逻辑和SRAM晶体管具有非压缩应力的ILD，P沟道逻辑晶体管ILD具有压缩应力，P沟道SRAM晶体管至少具有比P沟道逻辑晶体管更小的压缩应力，即P沟道SRAM 晶体管可以是压缩的，但是比P沟道逻辑晶体管更小，可以被放宽，或者可以是拉伸的。 P沟道SRAM晶体管的集成电路具有比P沟道逻辑晶体管更低的迁移率是有益的。具有较低移动性的P沟道SRAM晶体管导致更好的写入性能; 在更低的电源电压下更好地写入时间或写入裕度。

10. 发明授权

US5970349A Semiconductor device having one or more asymmetric background dopant regions and method of manufacture thereof 有权
标题翻译：具有一个或多个不对称背景掺杂剂区域的半导体器件及其制造方法
公开(公告)号：US5970349A
公开(公告)日：1999-10-19
申请号：US139179
申请日：1998-08-24
申请人： Jon Cheek , Mark I. Gardner , Michael Duane
发明人： Jon Cheek , Mark I. Gardner , Michael Duane
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66659 , H01L29/1083
摘要： Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a patterned mask with wider openings than conventional masks while substantially maintaining device performance. This can, for example, facilitate the fabrication process and allow greater flexibility in the choice of photolithography tools.
摘要翻译：提供具有一个或多个不对称背景掺杂剂区域的半导体器件及其制造方法。可以使用具有比常规掩模更宽的开口的图案化掩模来形成不对称背景掺杂区域，同时基本上保持器件性能。例如，这可以促进制造工艺并且允许在光刻工具的选择中具有更大的灵活性。

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