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1. 发明授权

US06300205B1 Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions 有权
标题翻译：制造具有自对准有源，轻掺杂漏极和卤区的半导体器件的方法
公开(公告)号：US06300205B1
公开(公告)日：2001-10-09
申请号：US09193262
申请日：1998-11-18
申请人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
发明人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.
摘要翻译：制造半导体器件的一种方法包括在衬底上形成栅电极并在栅电极的侧壁上形成间隔物。然后，使用第一掺杂剂材料，在衬底中形成有源区并与间隔物相邻，但与栅电极间隔开。使用不同于第一掺杂剂材料的导电类型的第二掺杂剂材料，在间隔物下方的衬底中形成晕圈区域并与有源区相邻。可以通过相对于衬底的表面以相对小于90°的角度将第二掺杂剂区域注入到衬底中来形成晕圈区域。然后去除间隔物的一部分，并且使用与第一掺杂剂材料相同的导电类型的第三掺杂剂材料，在邻近有源区和栅电极的衬底中形成轻掺杂区域，并且比晕区浅。

2. 发明授权

US6114211A Semiconductor device with vertical halo region and methods of manufacture 有权
标题翻译：具有垂直卤区的半导体器件及其制造方法
公开(公告)号：US6114211A
公开(公告)日：2000-09-05
申请号：US195336
申请日：1998-11-18
申请人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
发明人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
IPC分类号： H01L21/336 , H01L29/10
CPC分类号： H01L29/66492 , H01L29/1083 , H01L29/6653 , H01L29/6659
摘要： One method of forming a semiconductor device includes forming a gate electrode on a substrate and then forming a spacer adjacent to a sidewall of the gate electrode. An active region is formed in the substrate adjacent to the spacer and spaced apart from the gate electrode using a first dopant material of a first conductivity type. A protecting layer is formed over the active region and adjacent to the spacer. At least a portion of the spacer is then removed to form an opening between the protecting layer and the gate electrode. In some instances, the spacer may be formed by independent deposition of two different materials (e.g., silicon nitride and silicon dioxide), one of which can be selectively removed with respect to the other. A lightly-doped region is formed in the substrate adjacent to the gate electrode using a second dopant material of the first conductivity type. This lightly-doped region may be formed, for example, prior to formation of the spacer, between the formation of two portions of the spacer, or after removing at least a portion of the spacer. A halo region is formed through the opening resulting from removing a portion of the spacer. The halo region is deeper in the substrate than the lightly-doped region and is adjacent to the active region. The halo region is formed using a third dopant material of a conductivity type different than the first conductivity type.
摘要翻译：形成半导体器件的一种方法包括在衬底上形成栅电极，然后形成与栅电极的侧壁相邻的间隔物。使用第一导电类型的第一掺杂剂材料，在与衬垫相邻的衬底中形成有源区，并与栅电极间隔开。保护层形成在有源区上并与隔片相邻。然后去除间隔物的至少一部分以在保护层和栅电极之间形成开口。在一些情况下，可以通过独立沉积两种不同材料（例如，氮化硅和二氧化硅）来形成隔离物，其中一种可以相对于另一种材料选择性地去除。使用第一导电类型的第二掺杂剂材料在与栅电极相邻的衬底中形成轻掺杂区域。该轻掺杂区域例如可以在形成间隔物之前，在间隔物的两个部分的形成之间或在移除间隔物的至少一部分之后形成。通过从隔离物的一部分去除而形成的晕圈形成。卤素区域在衬底中比轻掺杂区域更深，并且与有源区域相邻。卤素区域是使用不同于第一导电类型的导电类型的第三掺杂剂材料形成的。

3. 发明授权

US6074906A Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers 失效
标题翻译：具有使用多个间隔物形成的源/漏区的互补金属氧化物半导体器件
公开(公告)号：US6074906A
公开(公告)日：2000-06-13
申请号：US958534
申请日：1997-10-27
申请人： Jon Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864
摘要： A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively. A third n-type dopant is selectively implanted into the NMOS active region using the second NMOS spacer as a mask to form a third n-doped region deeper than the second n-doped region in the NMOS active region. A second p-type dopant is selectively implanted into the PMOS active region using the second PMOS spacer as a mask to form a second p-doped region in the PMOS active region deeper than the first p-doped region.
摘要翻译：具有使用多个间隔物形成的NMOS源极/漏极区域的CMOS半导体器件具有至少一个NMOS区域和至少一个PMOS区域。第一n型掺杂剂被选择性地注入到与NMOS栅电极相邻的衬底的NMOS有源区中，以在NMOS有源区中形成第一n掺杂区。第一NMOS间隔物形成在NMOS栅电极的侧壁和PMOS栅电极的侧壁上的第一PMOS间隔物上。使用第一NMOS间隔物作为掩模，将第二n型掺杂剂选择性地注入NMOS有源区。使用第一PMOS间隔物作为掩模将p型掺杂剂选择性地注入PMOS有源区，以在PMOS有源区中形成第一p掺杂区。分别与第一NMOS间隔物和第一PMOS间隔物相邻地形成第二NMOS间隔物和第二PMOS间隔物。使用第二NMOS间隔物作为掩模，将第三n型掺杂剂选择性地注入NMOS有源区，以形成比NMOS有源区中的第二n掺杂区更深的第三n掺杂区。使用第二PMOS间隔物作为掩模将第二p型掺杂剂选择性地注入到PMOS有源区中，以在PMOS有源区中形成比第一p掺杂区更深的第二p掺杂区。

4. 发明授权

US06979878B1 Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites 失效
标题翻译：隔离结构在隔离槽的顶角处注入硅原子填充空位和间隙位置
公开(公告)号：US06979878B1
公开(公告)日：2005-12-27
申请号：US09217213
申请日：1998-12-21
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。

5. 发明授权

US6162688A Method of fabricating a transistor with a dielectric underlayer and device incorporating same 有权
标题翻译：制造具有电介质底层的晶体管的方法和结合其的器件
公开(公告)号：US6162688A
公开(公告)日：2000-12-19
申请号：US231427
申请日：1999-01-14
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/266 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/06 , H01L29/49 , H01L29/51 , H01L29/786 , H01L21/00
CPC分类号： H01L21/28194 , H01L21/266 , H01L21/268 , H01L21/28158 , H01L21/28202 , H01L21/823842 , H01L27/0688 , H01L29/4908 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545 , H01L29/66757 , H01L29/78636
摘要： A method is provided for fabricating a transistor, the method including forming a dielectric layer above a structure, forming a first polysilicon layer above the dielectric layer and forming a sacrificial region above the first polysilicon layer. The method also includes forming a second polysilicon layer above the first polysilicon layer and adjacent the sacrificial region. The method further includes removing the sacrificial region to form an opening in the second polysilicon layer, the opening having sidewalls, and forming dielectric spacers on the sidewalls of the opening. In addition, the method includes forming a gate dielectric within the opening above the first polysilicon layer and forming a gate conductor above the gate dielectric.
摘要翻译：提供了一种用于制造晶体管的方法，所述方法包括在结构之上形成电介质层，在电介质层上方形成第一多晶硅层，并在第一多晶硅层上方形成牺牲区域。该方法还包括在第一多晶硅层上形成第二多晶硅层并且邻近牺牲区。该方法还包括去除牺牲区域以在第二多晶硅层中形成开口，该开口具有侧壁，并在开口的侧壁上形成电介质间隔物。此外，该方法包括在第一多晶硅层上方的开口内形成栅极电介质，并在栅极电介质上方形成栅极导体。

6. 发明授权

US6040607A Self aligned method for differential oxidation rate at shallow trench isolation edge 失效
标题翻译：浅沟槽隔离边缘微分氧化率自对准方法
公开(公告)号：US6040607A
公开(公告)日：2000-03-21
申请号：US928607
申请日：1998-02-23
申请人： Derick J. Wristers , H. Jim Fulford , Mark I. Gardner
发明人： Derick J. Wristers , H. Jim Fulford , Mark I. Gardner
IPC分类号： H01L21/762 , H01L27/02 , H01L29/68
CPC分类号： H01L21/76237
摘要： A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the proximal portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.
摘要翻译：提供其中在半导体衬底中形成至少一个隔离结构的半导体工艺。氧离子种类被引入半导体衬底的靠近隔离结构的部分，优选通过使用离子注入到倾斜或倾斜的衬底中。然后在半导体衬底的上表面上形成栅介质层。在半导体衬底的近端部分存在含氧物质增加了近端部分相对于远离隔离结构的衬底部分的氧化速率的氧化速率。以这种方式，在半导体衬底的近端部分上的栅极电介质的第一厚度大于半导体衬底的剩余部分上的栅极氧化物层的第二厚度。与隔离沟槽的不连续性相邻的增加的氧化物厚度减小了跨过氧化物的电场。

7. 发明授权

US5994175A High performance MOSFET with low resistance design 失效
标题翻译：具有低电阻设计的高性能MOSFET
公开(公告)号：US5994175A
公开(公告)日：1999-11-30
申请号：US924781
申请日：1997-09-05
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A manufacturing process in which semiconductor transistors are fabricated using a fluorine or nitrogen implant into the n-channel regions and an amorphization implant to beneficially limit the spreading of the source/drain impurity distributions thereby decreasing the junction depth and increasing the sheet resistance of the source/drain regions. Broadly speaking, a gate dielectric layer is formed on a semiconductor substrate. First and second conductive gate structures are then formed on an upper surface of the gate dielectric layer. The first conductive gate is positioned over the p-well region while the second conductive gate is positioned over the n-well region. An n-channel mask is then formed on the substrate and a first impurity distribution is introduced into the p-well regions. The first impurity distribution preferably includes a species of fluorine or nitrogen. A n-type impurity distribution is then introduced into the p-well regions of the semiconductor substrate. A p-channel mask is then formed on the semiconductor substrate. After the p-channel mask is formed, a p-type impurity distribution such as boron is introduced into the n-well regions and into the second conductive gate structure. An electrically neutral impurity is then introduced into the semiconductor substrate to amorphize the semiconductor substrate to limit the subsequent redistribution of source/drain impurity distributions thereby resulting in the formation of shallow junctions. Thereafter, spacer structures are formed on sidewalls of the first and second conductive gate structures, and forming the spacer structures, n+ and p+ source/drain impurity distributions are introduced into the p and n well regions of the semiconductor substrate respectively.
摘要翻译：使用氟或氮注入到n沟道区域中制造半导体晶体管的制造工艺和非晶化注入，以有利地限制源极/漏极杂质分布的扩展，从而减小结深度并增加源极的薄层电阻 /漏区。广义地说，在半导体衬底上形成栅介质层。然后在栅介质层的上表面上形成第一和第二导电栅极结构。第一导电栅极位于p阱区上方，而第二导电栅极位于n阱区上方。然后在衬底上形成n沟道掩模，并将第一杂质分布引入p阱区。第一杂质分布优选包括一种氟或氮的种类。然后将n型杂质分布引入半导体衬底的p阱区。然后在半导体衬底上形成p沟道掩模。在形成p沟道掩模之后，诸如硼的p型杂质分布被引入n阱区并进入第二导电栅极结构。然后将电中性杂质引入半导体衬底中以使半导体衬底非晶化，以限制随后的源/漏杂质分布的再分配，从而导致形成浅结。此后，在第一和第二导电栅极结构的侧壁上形成间隔结构，并且形成间隔结构，将n +和p +源极/漏极杂质分布分别引入半导体衬底的p阱区和n阱区。

8. 发明授权

US06204148B1 Method of making a semiconductor device having a grown polysilicon layer 有权
标题翻译：制造具有生长的多晶硅层的半导体器件的方法
公开(公告)号：US06204148B1
公开(公告)日：2001-03-20
申请号：US09329843
申请日：1999-06-11
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L2176
CPC分类号： H01L29/66583
摘要： A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width. A method for partially forming a semiconductor device includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls. The first width of the opening is reduced to a second width by growing a layer of polysilicon adjacent at least a portion of the sidewalls of the opening.
摘要翻译：部分形成的半导体器件包括衬底，第一层，多晶硅层和生长的多晶硅层。第一层位于衬底的至少一部分上方。多晶硅层位于第一层的至少一部分的上方，并且其中形成有第一开口。第一开口具有由多个侧壁限定的第一宽度。多晶硅生长层位于至少多个侧壁附近，并且生长的多晶硅层限定第二开口。第二开口具有第二宽度，第二宽度小于第一宽度。部分形成半导体器件的方法包括在衬底的至少一部分上方形成工艺层。在工艺层的至少一部分上方形成多晶硅层。在多晶硅层中形成开口，并且开口具有由多个侧壁限定的第一宽度。通过在开口的侧壁的至少一部分附近生长一层多晶硅，将开口的第一宽度减小到第二宽度。

9. 发明授权

US5854121A Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure 失效
标题翻译：半导体制造采用掺入沟槽隔离结构边缘的势垒原子
公开(公告)号：US5854121A
公开(公告)日：1998-12-29
申请号：US923184
申请日：1997-09-04
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/02233 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/31612 , H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 .ANG.. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure. The masking layer may prevent the barrier atoms from being incorporated into any other regions of the substrate.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的部分也被去除，使得间隔物的厚度在约0至200安培之间。然后将半导体形貌暴露于阻挡夹带气体并加热，使得势垒原子并入到紧邻沟槽隔离结构的有源区域的区域中。掩模层可以防止阻挡原子被结合到衬底的任何其它区域中。

10. 发明授权

US06433400B1 Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure 有权
标题翻译：半导体制造采用掺入沟槽隔离结构边缘的势垒原子
公开(公告)号：US06433400B1
公开(公告)日：2002-08-13
申请号：US09153753
申请日：1998-09-15
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L2936
CPC分类号： H01L21/02233 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/31612 , H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure. The masking layer may prevent the barrier atoms from being incorporated into any other regions of the substrate.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。然后将半导体形貌暴露于阻挡夹带气体并加热，使得势垒原子并入到紧邻沟槽隔离结构的有源区域的区域中。掩模层可以防止阻挡原子被结合到衬底的任何其它区域中。

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