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1. 发明授权

US06190981B1 Method for fabricating metal oxide semiconductor 有权
标题翻译：金属氧化物半导体的制造方法
公开(公告)号：US06190981B1
公开(公告)日：2001-02-20
申请号：US09243740
申请日：1999-02-03
申请人： Tony Lin , Jih-Wen Chou
发明人： Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/4983 , H01L29/4991 , H01L29/665
摘要： A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.
摘要翻译：描述了制造金属氧化物半导体晶体管的方法。提供其上具有隔离结构的基板。在衬底上形成栅氧化层。在栅氧化层上形成多晶硅层。图案化多晶硅层以在栅极氧化物层上形成栅极。在门的侧壁上形成偏移间隔物。通过离子注入在栅极两侧的衬底中形成源极/漏极延伸。绝缘间隔件形成在偏移间隔件的侧壁上。通过使用栅极，偏移间隔物和绝缘间隔物作为掩模的离子注入在衬底中形成源极/漏极区。在栅极和源极/漏极区域的表面上形成硅化物。在形成自对准硅胶后，去除偏移间隔物。在去除偏移间隔物之后，通过离子注入在源极/漏极延伸部下方的衬底中形成光晕掺杂区域。

2. 发明授权

US5914519A Air-gap spacer of a metal-oxide-semiconductor device 失效
标题翻译：金属氧化物半导体器件的气隙间隔物
公开(公告)号：US5914519A
公开(公告)日：1999-06-22
申请号：US9302
申请日：1998-01-20
申请人： Jih-Wen Chou , Tony Lin
发明人： Jih-Wen Chou , Tony Lin
IPC分类号： H01L21/336 , H01L29/49 , H01L29/78 , H01L29/14 , H01L29/76
CPC分类号： H01L29/66598 , H01L29/4983 , H01L29/4991 , H01L29/6659 , H01L29/7833
摘要： An air-gap spacer of a metal-oxide-semiconductor device comprises a spacer and a cross-sectional L-shaped air-gap. The spacer is adjacent to a sidewall of the gate electrode but not directly contacts to the gate electrode. The cross-sectional L-shaped air-gap is located between the spacer and the gate electrode and between the spacer and the substrate so that the spacer is separated from the gate electrode and the spacer is partially separated from the substrate.
摘要翻译：金属氧化物半导体器件的气隙间隔件包括间隔件和截面L形气隙。间隔物与栅电极的侧壁相邻，但不直接接触栅电极。横截面的L形气隙位于间隔件和栅电极之间，并且位于间隔件和衬底之间，使得间隔件与栅电极分离，并且间隔件与衬底部分地分离。

3. 发明授权

US06200870B1 Method for forming gate 有权
标题翻译：浇口形成方法
公开(公告)号：US06200870B1
公开(公告)日：2001-03-13
申请号：US09189355
申请日：1998-11-09
申请人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28061 , H01L21/28247
摘要： A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.
摘要翻译：用于形成提高栅极质量的栅极的方法包括在衬底上顺序地形成栅极氧化物层，多晶硅层，导电层和掩模层。此后，对掩模层，导电层，多晶硅层和栅极氧化物层进行图案化以形成栅极。然后，通过用氮阳离子的离子注入，在导电层的侧壁上形成用于增加栅极的热稳定性和化学稳定性的钝化层。氮阳离子通过离子注入在栅极氧化物层下方掺杂到衬底中，这可以改善磷离子的渗透。

4. 发明授权

US06174791B1 Method for a pre-amorphization 失效
标题翻译：前非晶化方法
公开(公告)号：US06174791B1
公开(公告)日：2001-01-16
申请号：US09276294
申请日：1999-03-25
申请人： Tony Lin , Jih-Wen Chou , C. C. Hsue
发明人： Tony Lin , Jih-Wen Chou , C. C. Hsue
IPC分类号： H01L21425
CPC分类号： H01L21/28518 , H01L21/26506 , H01L29/665
摘要： A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.
摘要翻译：一种用于在MOS晶体管的端子上形成非晶硅层的方法。该方法包括以下步骤：形成具有在MOS晶体管上暴露栅极多晶硅层的开口的掩模层。接下来，使用掩模层作为掩模，执行非活性离子注入操作，使得非活性离子注入到栅极多晶硅层中。此后，再次使用掩模层作为掩模，进行第一次重轰击操作，局部注入离子。最后，去除掩模层，然后进行第二次重轰击操作，全局注入离子。

5. 发明授权

US06165857A Method for forming a transistor with selective epitaxial growth film 有权
标题翻译：用选择性外延生长膜形成晶体管的方法
公开(公告)号：US06165857A
公开(公告)日：2000-12-26
申请号：US469008
申请日：1999-12-21
申请人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417
CPC分类号： H01L29/6659 , H01L21/28052 , H01L29/41775 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer. Next, the first dielectric layer is etched until upper surface of the gate and a portion of the substrate are exposed, wherein a part of the second dielectric layer is also etched accompanying with etching a part of the first dielectric layer. Further, second ions are implanted into the exposed substrate to form a source/drain region. A conductive layer is selectively formed on said over the exposed gate and source/drain. Finally, a self-aligned silicide layer is formed over the conductive layer.
摘要翻译：公开了选择性外延生长的新改进。在一个实施例中，本发明提供一种包括衬底的低功率金属氧化物半导体场效应晶体管（MOSFET）。接着，在基板上形成栅极氧化层。此外，在栅极氧化物层上沉积多晶硅层。图案化以蚀刻多晶硅层和栅极氧化物层以限定栅极。通过使用所述栅极作为硬掩模将第一离子注入到衬底中。接下来，衬垫氧化物覆盖在所得结构的整个暴露表面上。此外，适形的第一介电层和第二介电层以适当的顺序沉积在衬垫氧化物的上方。回蚀第二电介质层以在第一电介质层的侧壁上形成电介质间隔物。接下来，蚀刻第一电介质层直到栅极的上表面和衬底的一部分被暴露，其中第二电介质层的一部分也被蚀刻，同时蚀刻第一介电层的一部分。此外，将第二离子注入暴露的衬底中以形成源/漏区。在暴露的栅极和源极/漏极上的选择性地形成导电层。最后，在导电层上形成自对准的硅化物层。

6. 发明授权

US06297082B1 Method of fabricating a MOS transistor with local channel ion implantation regions 失效
标题翻译：用本地沟道离子注入区制造MOS晶体管的方法
公开(公告)号：US06297082B1
公开(公告)日：2001-10-02
申请号：US09383033
申请日：1999-08-25
申请人： Tony Lin , Alice Chao , Jih-Wen Chou
发明人： Tony Lin , Alice Chao , Jih-Wen Chou
IPC分类号： H01L218238
CPC分类号： H01L29/66537 , H01L21/823807 , H01L29/7833
摘要： A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming wells in the substrate, two implantation regions for providing a threshold voltage (VT) adjustment and an anti-punch through layer are formed respectively in a P-well and a N-well of the core region as well as a P-well and a N-well of the I/O region. The method involves forming a pattern mask on the gate oxide layer, wherein the pattern mask has an opening, which may be a channel that corresponds to the P-well of the core region. With the pattern mask serving as an ion implantation mask, two implantation regions for providing the VT adjustment and the anti-punch through layer are formed in the P-well of the core region. After the pattern mask is removed, the steps described above are repeated in order to form implantation regions in other regions, but the sequence of the steps can be swapped around at will. The subsequent process for the MOS transistor is then performed.
摘要翻译：金属氧化物半导体（MOS）晶体管的制造方法涉及在核心区域和输入/输出（I / O）区域上形成不同厚度的栅极氧化物层。在衬底中形成阱之后，分别在芯区的P阱和N阱以及P阱中形成用于提供阈值电压（VT）调整和抗穿通层的两个注入区域和I / O区域的N阱。该方法包括在栅极氧化物层上形成图案掩模，其中图案掩模具有开口，该开口可以是对应于核心区域的P阱的沟道。利用图案掩模作为离子注入掩模，在核心区域的P阱中形成用于提供VT调整和抗穿透层的两个注入区域。在去除图案掩模之后，重复上述步骤以在其它区域中形成植入区域，但是步骤的顺序可以随意地交换。然后执行MOS晶体管的后续处理。

7. 发明授权

US5950090A Method for fabricating a metal-oxide semiconductor transistor 失效
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US5950090A
公开(公告)日：1999-09-07
申请号：US193217
申请日：1998-11-16
申请人： Coming Chen , Tony Lin , Jih-Wen Chou
发明人： Coming Chen , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762 , H01L29/417
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/76224 , H01L29/66545 , H01L29/41775
摘要： A method for fabricating a MOS transistor device is provided. The method contains sequentially forming an oxide layer, a polysilicon layer, and a cap layer over a semiconductor substrate. Patterning the oxide layer, the polysilicon layer, the cap layer, and the substrate forms a trench opening in the substrate. A shallow trench isolation (STI) structure is formed by filling the opening with insulating material. A first-stage gate structure is formed on the substrate by patterning the oxide layer, the polysilicon layer, and the cap layer. A top portion of the STI structure above the substrate surface is exposed. A light ion implantation is performed to form a lightly doped region. Several spacers are respectively formed on each sidewall of the first-stage gate structure and each exposed sidewall of the STI structure. A heavy ion implantation process is performed to form interchangeable source/drain regions at each side of the first-stage gate structure. The cap layer is removed to leave an opening. A conductive layer is formed over the substrate and is planarized so that a remaining portion of the conductive layer fills the opening to serve as a gate metal layer. The remaining portion of the conductive layer also fills a free space between the spacers above the interchangeable source/drain regions to form several contact plugs. A dielectric layer is formed over the substrate with second contact plugs, respectively electrically coupled to the gate metal layer and the first contact plugs.
摘要翻译：提供一种用于制造MOS晶体管器件的方法。该方法包括在半导体衬底上顺序形成氧化物层，多晶硅层和覆盖层。对氧化物层，多晶硅层，盖层和衬底进行图案化，在衬底中形成沟槽开口。通过用绝缘材料填充开口形成浅沟槽隔离（STI）结构。通过图案化氧化物层，多晶硅层和盖层，在衬底上形成第一级栅极结构。暴露基板表面上方的STI结构的顶部。进行轻离子注入以形成轻掺杂区域。在STI结构的第一级栅极结构的每个侧壁和每个暴露的侧壁上分别形成几个间隔物。执行重离子注入工艺以在第一级栅极结构的每一侧形成可互换的源/漏区。盖层去除以留下开口。导电层形成在衬底上并被平坦化，使得导电层的剩余部分填充开口以用作栅极金属层。导电层的剩余部分还填充可互换的源极/漏极区之间的间隔物之间的自由空间，以形成多个接触插塞。在基板上形成介电层，第二接触插塞分别电耦合到栅极金属层和第一接触插塞。

8. 发明授权

US06503807B2 MOS transistor with two empty side slots on its gate and its method of formation 失效
标题翻译： MOS晶体管在其栅极上具有两个空侧槽，其形成方法
公开(公告)号：US06503807B2
公开(公告)日：2003-01-07
申请号：US09803893
申请日：2001-03-13
申请人： Chin-Lai Chen , Tony Lin , Jih-Wen Chou
发明人： Chin-Lai Chen , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/4991 , H01L29/4983 , H01L29/665 , H01L29/66537 , H01L29/66553 , H01L29/66583
摘要： A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrate between the drain and the source. The gate includes a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer. The transistor includes at least one empty side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.
摘要翻译： MOS晶体管包括基板，绝缘层，栅极和电介质层。衬底包括分别位于衬底的表面上的漏极和源极。绝缘层位于漏极和源极之间的衬底表面上。栅极包括位于具有底侧，顶侧，左侧和右侧的绝缘层上的导电层和位于导电层顶侧的金属硅化物层，其中金属硅化物层的宽度大于导电层底面的面积。电介质层覆盖漏极，源极和金属硅化物层。晶体管包括至少一个位于电介质层与金属硅化物层下方的导电层的左侧或右侧之间的空侧槽。

9. 发明授权

US06350656B1 SEG combined with tilt side implant process 失效
标题翻译： SEG结合倾斜侧植入过程
公开(公告)号：US06350656B1
公开(公告)日：2002-02-26
申请号：US09495249
申请日：2000-01-31
申请人： Jung-Chun Lin , Tony Lin , Jih-Wen Chou
发明人： Jung-Chun Lin , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/2652 , H01L21/26586 , H01L29/41783 , H01L29/665
摘要： A SEG combined with tilt implant method for forming semiconductor device is disclosed. The method includes providing a semiconductor structure which comprises an active area in between isolation regions in a substrate with the active area having a gate electrode formed thereon, wherein a spacer is formed on the sidewall of said gate electrode. Then, selective epitaxial growth regions are formed on the active area and the gate electrode. Next, the active area is implanted with an angle to form source/drain regions beside the bottom edge of the gate electrode. Then, the salicide process and backend processes are performed.
摘要翻译：公开了一种结合用于形成半导体器件的倾斜植入方法的SEG。该方法包括提供半导体结构，该半导体结构包括在衬底中的隔离区域之间的有源区域，其中有源区域上形成有栅电极，其中间隔物形成在所述栅电极的侧壁上。然后，在有源区和栅电极上形成选择性外延生长区。接下来，以一角度植入有源区域，以在栅电极的底部边缘旁边形成源极/漏极区域。然后，执行自杀化合物处理和后端处理。

10. 发明授权

US06274450B1 Method for implementing metal oxide semiconductor field effect transistor 失效
标题翻译：金属氧化物半导体场效应晶体管的实现方法
公开(公告)号：US06274450B1
公开(公告)日：2001-08-14
申请号：US09398733
申请日：1999-09-17
申请人： Tony Lin , Coming Chen , Jih-Wen Chou
发明人： Tony Lin , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/4966 , H01L29/4983 , H01L29/4991 , H01L29/66507 , H01L29/6653 , H01L29/66545
摘要： A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer. Seventh, the spacer is removed and both a halo and a source drain extension are formed in substrate. Finally, a third dielectric layer is formed on second dielectric layer. Obviously, one main characteristic of the invention is both source drain extension and halo are formed after a plurality of thermal processes such as deposition, annealing and formation of salicide.
摘要翻译：公开了一种用于制造金属氧化物半导体场效应晶体管的方法。金属氧化物半导体场效应晶体管通过具体的制造工艺形成，有效地防止了热损伤的缺点。根据该方法，首先提供基板。第二，在衬底中形成隔离和阱，然后依次在衬底上形成第一介电层，导电层和抗反射涂层。第三，在衬底上形成栅极，然后在衬底中形成源极和漏极，并在衬底上形成间隔物。第四，源极和漏极都被退火，然后在源极和漏极上形成第一自对准硅化物。第五，在基板上形成第二电介质层并进行平面化处理，其中防反射涂层被完全去除并且导电层被部分去除。第六，在导电层上形成第二个自对准硅化物。第七，去除间隔物，并且在衬底中形成卤素和源极漏极延伸。最后，在第二电介质层上形成第三电介质层。显然，本发明的一个主要特征是源极漏极延伸，并且在诸如沉积，退火和形成硅化物的多个热处理之后形成卤素。

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