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1. 发明授权

US06174791B1 Method for a pre-amorphization 失效
标题翻译：前非晶化方法
公开(公告)号：US06174791B1
公开(公告)日：2001-01-16
申请号：US09276294
申请日：1999-03-25
申请人： Tony Lin , Jih-Wen Chou , C. C. Hsue
发明人： Tony Lin , Jih-Wen Chou , C. C. Hsue
IPC分类号： H01L21425
CPC分类号： H01L21/28518 , H01L21/26506 , H01L29/665
摘要： A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.
摘要翻译：一种用于在MOS晶体管的端子上形成非晶硅层的方法。该方法包括以下步骤：形成具有在MOS晶体管上暴露栅极多晶硅层的开口的掩模层。接下来，使用掩模层作为掩模，执行非活性离子注入操作，使得非活性离子注入到栅极多晶硅层中。此后，再次使用掩模层作为掩模，进行第一次重轰击操作，局部注入离子。最后，去除掩模层，然后进行第二次重轰击操作，全局注入离子。

2. 发明授权

US06211027B1 Method for manufacturing PMOS transistor 失效
标题翻译：制造PMOS晶体管的方法
公开(公告)号：US06211027B1
公开(公告)日：2001-04-03
申请号：US09444278
申请日：1999-11-19
申请人： Tony Lin , C. C. Hsue
发明人： Tony Lin , C. C. Hsue
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/266 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/6659
摘要： A method for manufacturing a PMOS transistor. A gate terminal is formed over a substrate. Spacers are formed on the sidewalls of the gate terminal. A source/drain terminal is formed in the substrate on each side of the gate terminal, and then a metal silicide layer is formed over the top surface of the gate terminal and the substrate. The spacers are next removed. Using the metal silicide layer as a mask, a source/drain extension region is formed in the substrate between the gate terminal and the source/drain terminal. Similarly, using the metal silicide layer as a mask, an anti-punchthrough region is form in the substrate interior under the source/drain extension region.
摘要翻译：一种用于制造PMOS晶体管的方法。栅极端子形成在基板上。隔板形成在栅极端子的侧壁上。源极/漏极端子形成在栅极端子的每一侧上的衬底中，然后在栅极端子和衬底的顶表面上形成金属硅化物层。接下来移除间隔物。使用金属硅化物层作为掩模，在栅极端子和源极/漏极端子之间的衬底中形成源极/漏极延伸区域。类似地，使用金属硅化物层作为掩模，在源极/漏极延伸区域下方的衬底内部形成抗穿透区域。

3. 发明授权

US06391760B1 Method of fabricating local interconnect 失效
标题翻译：制造局部互连的方法
公开(公告)号：US06391760B1
公开(公告)日：2002-05-21
申请号：US09208734
申请日：1998-12-08
申请人： C. C. Hsue , Wei-Chung Chen
发明人： C. C. Hsue , Wei-Chung Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76895
摘要： A method of forming a local interconnect is provided. A semiconductor is provided. An isolation structure, a transistor and a conductive layer are formed on the substrate. A dielectric layer with an opening is formed over the substrate. A part of the dielectric layer is removed by a photolithography and etching process to form a via opening to expose a part of the gate of the transistor or a part of the conductive layer. A conformal barrier layer is formed in the via opening and overflows the dielectric layer. A conductive plug is formed in the via opening. The barrier layer is patterned to form a local interconnect.
摘要翻译：提供了形成局部互连的方法。提供半导体。在衬底上形成隔离结构，晶体管和导电层。在衬底上形成具有开口的电介质层。通过光刻和蚀刻工艺去除介电层的一部分，以形成通孔以暴露晶体管的一部分栅极或导电层的一部分。在通路孔中形成保形阻挡层，并使介质层溢出。导电塞形成在通孔开口中。将阻挡层图案化以形成局部互连。

4. 发明授权

US06313006B1 Method of field implantation 失效
标题翻译：现场植入方法
公开(公告)号：US06313006B1
公开(公告)日：2001-11-06
申请号：US09048637
申请日：1998-03-26
申请人： C. C. Hsue , Sun-Chieh Chien
发明人： C. C. Hsue , Sun-Chieh Chien
IPC分类号： H01L2176
CPC分类号： H01L27/10888 , H01L21/761 , H01L21/823807 , H01L27/10811 , H01L27/10855 , H01L29/1083
摘要： A method of field implantation. Using a photo-resist layer as a mask, a substrate is implanted with ions to forming a selectively distributed ion field.
摘要翻译：一种野外植入的方法。使用光阻层作为掩模，用离子注入基板以形成选择性分布的离子场。

5. 发明授权

US6026012A Dual port random access memory 有权
标题翻译：双端口随机存取存储器
公开(公告)号：US6026012A
公开(公告)日：2000-02-15
申请号：US222008
申请日：1998-12-30
申请人： C. C. Hsue
发明人： C. C. Hsue
IPC分类号： G11C8/16 , G11C7/00
CPC分类号： G11C8/16
摘要： A dual port random access memory (RAM). The dual port random access memory includes four N-MOS transistors and four P-MOS transistors. Both the N-MOS and the P-MOS transistors are used as pass gates. More specifically, two N-MOS transistors are used as pass gate for a set of bit lines and two P-MOS transistors are used as a pass gate to another set of bit lines.
摘要翻译：双端口随机存取存储器（RAM）。双端口随机存取存储器包括四个N-MOS晶体管和四个P-MOS晶体管。 N-MOS和P-MOS晶体管都用作通孔。更具体地，使用两个N-MOS晶体管作为一组位线的通孔，并且使用两个P-MOS晶体管作为另一组位线的通过栅极。

6. 发明授权

US5981334A Method of fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US5981334A
公开(公告)日：1999-11-09
申请号：US965326
申请日：1997-11-06
申请人： Sun-Chieh Chien , Jason Jenq , C. C. Hsue
发明人： Sun-Chieh Chien , Jason Jenq , C. C. Hsue
IPC分类号： H01L21/02 , H01L21/70 , H01L21/00
CPC分类号： H01L28/82 , H01L28/84 , H01L28/91
摘要： A method for fabricating DRAM capacitor which includes forming a transistor having a source/drain regions and a gate electrode above a silicon substrate; then, forming sequentially a stack of layers including a first insulating layer, a second insulating layer, a third insulating layer and a hard mask layer over the transistor; subsequently, patterning and etching the hard mask layer. Thereafter, an oxide layer is formed over the hard mask layer, and then portions of the layers are etched to form a capacitor region over the oxide layer and a contact opening exposing a portion of the source/drain region. In the subsequent step, a conducting layer is formed over the oxide layer, the hard mask layer, the sidewalls of the contact opening and the exposed portion of the source/drain region. Next, a polishing method is used to remove the conducting layer above the oxide layer, and then the oxide layer is removed to form a lower electrode. A dielectric layer is then formed over the lower electrode, and finally an upper electrode layer is formed over the dielectric layer.
摘要翻译：一种用于制造DRAM电容器的方法，其包括在硅衬底上形成具有源极/漏极区域和栅极电极的晶体管; 然后在晶体管上依次形成包括第一绝缘层，第二绝缘层，第三绝缘层和硬掩模层的层叠层; 随后，对硬掩模层进行图案化和蚀刻。此后，在硬掩模层之上形成氧化物层，然后蚀刻这些层的一部分以在氧化物层上形成电容器区域，以及暴露源极/漏极区域的一部分的接触开口。在随后的步骤中，在氧化物层，硬掩模层，接触开口的侧壁和源极/漏极区域的暴露部分之上形成导电层。接下来，使用抛光方法去除氧化物层上方的导电层，然后除去氧化物层以形成下电极。然后在下电极上形成电介质层，最后在电介质层上形成上电极层。

7. 发明授权

US06221710B1 Method of fabricating capacitor 有权
标题翻译：制造电容器的方法
公开(公告)号：US06221710B1
公开(公告)日：2001-04-24
申请号：US09222621
申请日：1998-12-29
申请人： C. C. Hsue , Wei-Chung Chen
发明人： C. C. Hsue , Wei-Chung Chen
IPC分类号： H01L218234
CPC分类号： H01L28/75 , H01L27/10852 , H01L28/55
摘要： A method of fabricating a capacitor on a semiconductor substrate. A barrier layer is formed over the substrate to serve as a bottom electrode of the capacitor. A dielectric layer is formed on the barrier layer. An upper electrode is formed on the dielectric layer. In addition, the method can be used in a dynamic random access memory.
摘要翻译：一种在半导体衬底上制造电容器的方法。在衬底上形成阻挡层以用作电容器的底部电极。在阻挡层上形成介电层。在电介质层上形成上电极。另外，该方法可以用于动态随机存取存储器。

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