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1. 发明授权

US5794070A Method and apparatus for fast DMA transfer on an industry standard architecture (ISA) bus 失效
标题翻译：用于工业标准架构（ISA）总线上快速DMA传输的方法和装置
公开(公告)号：US5794070A
公开(公告)日：1998-08-11
申请号：US730777
申请日：1996-10-16
申请人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
发明人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.
摘要翻译：计算机系统包括直接存储器访问（DMA）传送单元和通过外部总线耦合的多个DMA设备。 DMA传送单元为多个DMA设备实现DMA传输。 DMA传输单元包含DMA控制器，总线仲裁器和总线控制器。 DMA控制器和总线控制器产生一个两个时钟周期的DMA传输。为了实现双时钟周期DMA传输，请求的DMA设备与DMA控制器建立DMA传输，使得在第一时钟周期期间断言DACK＃信号。在第二个时钟周期内，DMA控制器设置存储器地址。在第三个时钟周期内，总线控制器转换外部总线上的命令信号。在断言命令信号时，有效数据在外部总线上被断言。对于需求和块模式操作，在两个时钟周期的DMA传输中执行额外的DMA传输。 DMA控制器和总线控制器也产生三个时钟周期的DMA传输。

2. 发明授权

US5664122A Method and apparatus for sequencing buffers for fast transfer of data between buses 失效
标题翻译：用于排序缓冲器的方法和装置，用于在总线之间快速传输数据
公开(公告)号：US5664122A
公开(公告)日：1997-09-02
申请号：US619092
申请日：1996-03-20
申请人： Jeffrey L. Rabe , Sathyamurthi Sadhasivan
发明人： Jeffrey L. Rabe , Sathyamurthi Sadhasivan
IPC分类号： G06F13/40 , G06F12/00 , G06F13/00
CPC分类号： G06F13/4059
摘要： A buffer circuit for transferring data between a first slower narrower computer bus and a second wider faster computer bus which buffer circuit includes first and second buffers each capable of storing a plurality of bytes of data equivalent to the width of the second bus, a single address register for holding an address which represents data in either of the two buffers, the lowest order bit of the address register indicating to which one of the two buffers data is being written, first and second registers for storing indications of valid data in the first and second buffers, and a control circuit for controlling the filling of the first and the second buffers in accordance with the byte addresses furnished and the flushing of the first and the second buffers whenever a most significant byte of a buffer has valid data, whenever an attempt is made to write to a buffer address containing valid data, and whenever an attempt is made to load data to a buffer address different than an address in the address register so that sequences of bytes of data are typically accumulated in order in one buffer until an amount of data equal to that which may be transferred on the second wider faster bus is accumulated and then that buffer is flushed to the second wider faster bus while the other buffer is loaded with new data, and so that valid data is not overwritten even though non-sequential addresses are loaded.
摘要翻译：一种缓冲电路，用于在第一较窄较窄的计算机总线和第二更宽的计算机总线之间传送数据，该缓冲电路包括第一和第二缓冲器，每个缓冲器能够存储等同于第二总线的宽度的多个字节数据，单个地址注册用于保存表示两个缓冲器中的任一个中的数据的地址，地址寄存器的低位位指示正在写入两个缓冲器数据中的哪一个;第一和第二寄存器，用于存储第一和第二缓冲器数据中的有效数据的指示; 第二缓冲器，以及控制电路，用于当缓冲器的最高有效字节具有有效数据时，根据提供的字节地址和第一和第二缓冲器的刷新来控制第一和第二缓冲器的填充，被写入包含有效数据的缓冲地址，并且每当尝试将数据加载到不同于addre的缓冲地址 ss在地址寄存器中，使得数据字节序列通常在一个缓冲器中按顺序累积，直到数据量等于在第二较宽更快的总线上传送的数据量被累积，然后该缓冲器被刷新到第二个较宽的更快的总线，而另一个缓冲区加载新的数据，并且即使加载非顺序地址，有效数据也不会被覆盖。

3. 发明授权

US5761444A Method and apparatus for dynamically deferring transactions 失效
标题翻译：动态推迟交易的方法和装置
公开(公告)号：US5761444A
公开(公告)日：1998-06-02
申请号：US523385
申请日：1995-09-05
申请人： Jasmin Ajanovic , Robert N. Murdoch , Timothy M. Dobbins , Aditya Sreenivas , Stuart E. Sailer , Jeffrey L. Rabe
发明人： Jasmin Ajanovic , Robert N. Murdoch , Timothy M. Dobbins , Aditya Sreenivas , Stuart E. Sailer , Jeffrey L. Rabe
IPC分类号： G06F13/362 , G06F13/36
CPC分类号： G06F13/362
摘要： A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.
摘要翻译：公开了一种用于调节由计算机系统中的处理器在总线上发布的交易的延迟的方法和装置。总线事务记录器耦合到总线上，处理在总线上发出的事务的编码信号。当总线上发出待处理的事务请求时，耦合到总线的线路发送指示信号。当新的待处理事务在总线上等待时，CPU等待时间计时器会重新计算总线上的当前事务。当等待时间超过预定时间时，CPU等待时间会输出到期信号。交易处理器单元耦合到总线事务记录器，线路和CPU等待时间计时器。交易处理器单元在事务处理器接收到指示等待发送在总线上的待处理事务的指示信号时，在总线上发出的交易的编码信号指示发出的交易总线是延迟的候选者，当CPU等待时间输出到期信号时。

4. 发明授权

US5546548A Arbiter and arbitration process for a dynamic and flexible prioritization 失效
标题翻译：仲裁和仲裁程序，以动态和灵活的优先级排序
公开(公告)号：US5546548A
公开(公告)日：1996-08-13
申请号：US40518
申请日：1993-03-31
申请人： Ray Chen , Jeffrey L. Rabe
发明人： Ray Chen , Jeffrey L. Rabe
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： A programmable arbiter providing for dynamic configuration of prioritization schemes is implemented using a simple, but effective structure. One or more arbiter banks are structured in a cascading manner. Each arbiter bank receives a predetermined number of the set of bus requests to be arbitrated. Each bank is separately programmed to provide a rotating or fixed priority scheme to evaluate the priority of the bus requests. Thus by separately programming the arbiter banks to operate in a fixed priority or rotating priority manner, a flexible, programmable arbiter is created which can operate according to a fixed, rotating or hybrid priority scheme and is adaptable to a variety of applications.
摘要翻译：使用简单但有效的结构来实现提供优先化方案的动态配置的可编程仲裁器。一个或多个仲裁组是以级联方式组织的。每个仲裁器银行接收一组预定数量的要仲裁的总线请求。每个银行单独编程以提供旋转或固定优先级方案来评估总线请求的优先级。因此，通过单独编程仲裁器组以固定优先级或旋转优先级方式操作，创建灵活的可编程仲裁器，其可以根据固定，旋转或混合优先级方案操作并且可适用于各种应用。

5. 发明授权

US5655127A Method and apparatus for control of power consumption in a computer system 失效
标题翻译：用于控制计算机系统中功耗的方法和装置
公开(公告)号：US5655127A
公开(公告)日：1997-08-05
申请号：US612673
申请日：1996-03-08
申请人： Jeffrey L. Rabe , Zohar Bogin , Ajay V. Bhatt , James P. Kardach , Nilesh V. Shah
发明人： Jeffrey L. Rabe , Zohar Bogin , Ajay V. Bhatt , James P. Kardach , Nilesh V. Shah
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/3287 , Y02B60/1282 , Y02B60/32
摘要： A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.
摘要翻译：一种具有响应低功率模式和全功率工作模式的计算机系统。计算机系统包括功率消耗控制器，处理器和通信设备。功率消耗控制器响应于低功率事件或完全运行的事件而产生中断信号。功耗控制器还产生时钟控制信号。时钟控制信号在全功率工作模式期间被断言，并且在低功率操作模式期间另行断言第一持续时间并且断言第二持续时间。响应于断言的时钟控制信号，处理器将内部时钟信号抑制到处理器内的至少一个功能块，并且响应于无效时钟控制信号，处理器将内部时钟信号发送到内部时钟信号中的至少一个功能块处理器。通过在低功率操作模式期间将内部时钟信号发送到处理器内的至少一个功能块，处理器可以在低功率操作模式期间响应来自通信设备的通信信号。

6. 发明授权

US07376782B2 Index/data register pair for indirect register access 有权
标题翻译：用于间接寄存器访问的索引/数据寄存器对
公开(公告)号：US07376782B2
公开(公告)日：2008-05-20
申请号：US11172254
申请日：2005-06-29
申请人： Jasper Balraj , Geetani R. Edirisooriya , John P. Lee , Robert Strong , Jeffrey L. Rabe , Amber Huffman , Daniel Nemiroff , Rajeev Nalawadi
发明人： Jasper Balraj , Geetani R. Edirisooriya , John P. Lee , Robert Strong , Jeffrey L. Rabe , Amber Huffman , Daniel Nemiroff , Rajeev Nalawadi
IPC分类号： G06F12/00
CPC分类号： G06F9/4401
摘要： A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.
摘要翻译：计算机系统通过使用索引寄存器和数据寄存器在实模式操作期间提供对第一寄存器的访问，其中索引寄存器和数据寄存器位于实模式存储器空间中，并且第一寄存器位于实模式之外内存空间。

7. 发明授权

US07343469B1 Remapping I/O device addresses into high memory using GART 有权
标题翻译：使用GART将I / O设备地址重新映射到高内存中
公开(公告)号：US07343469B1
公开(公告)日：2008-03-11
申请号：US09667050
申请日：2000-09-21
申请人： Zohar Bogin , Jeffrey L. Rabe
发明人： Zohar Bogin , Jeffrey L. Rabe
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F12/1027
摘要： An address translation apparatus and method that can convert a limited-range memory address from a peripheral device to an expanded-range memory address on the fly. The invention can expand the limited address capability of a peripheral bus, such as a PCI bus with a 4 GB address range, to a much larger address capability, such as a 64 GB address range. This conversion can be performed on the fly by hardware, so that no appreciable delay in transfer time is created. The conversion can be performed by adding features to a conventional graphics controller interface, thus minimizing the impact on circuit complexity and system cost.
摘要翻译：一种地址转换装置和方法，其可以将有限范围的存储器地址从外围设备转换为扩展存储器地址。本发明可以将诸如具有4GB地址范围的PCI总线等外围总线的有限地址能力扩展到更大的地址能力，例如64GB的地址范围。这种转换可以由硬件在飞行中执行，因此不会产生明显的传输时间延迟。可以通过向传统图形控制器接口添加特征来实现转换，从而最小化对电路复杂性和系统成本的影响。

8. 发明授权

US5551044A Method and apparatus for interrupt/SMI# ordering 失效
标题翻译：中断/ SMI＃排序的方法和装置
公开(公告)号：US5551044A
公开(公告)日：1996-08-27
申请号：US349065
申请日：1994-12-01
申请人： Nilesh V. Shah , Jeffrey L. Rabe , Zohar Bogin
发明人： Nilesh V. Shah , Jeffrey L. Rabe , Zohar Bogin
IPC分类号： G06F13/24 , G06F13/00
CPC分类号： G06F13/24
摘要： A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.
摘要翻译：用于控制计算机系统中的中断请求信号传输的电路。输入接收来自外部组件的中断请求。耦合到输入的第一电路响应于来自外部组件的中断请求而生成信号。信号使处理器切换到完全运行模式。耦合到输入的第二电路响应于来自外部组件的中断请求，向处理器生成中断请求信号。耦合到第二电路的信号处理电路抑制中断请求信号到处理器的传输，直到信号被发送到处理器。

9. 发明授权

US07100032B2 Method and apparatus for identifying hardware compatibility and enabling stable software images 失效
标题翻译：用于识别硬件兼容性并启用稳定的软件映像的方法和装置
公开(公告)号：US07100032B2
公开(公告)日：2006-08-29
申请号：US10187222
申请日：2002-06-28
申请人： Jeffrey L. Rabe , Alberto J. Martinez , Serafin E. Garcia , Jackie Wensel
发明人： Jeffrey L. Rabe , Alberto J. Martinez , Serafin E. Garcia , Jackie Wensel
IPC分类号： G06F9/00
CPC分类号： G06F9/4401
摘要： An approach to selecting either an actual stepping revision ID value or a compatible revision ID value to be readable by a processor through a revision ID register.
摘要翻译：选择实际步进修订版本ID值或兼容修订版本ID值的方法，以便处理器通过修订ID寄存器读取。

10. 发明授权

US06983339B1 Method and apparatus for processing interrupts of a bus 失效
标题翻译：一种用于处理总线中断的方法和装置
公开(公告)号：US06983339B1
公开(公告)日：2006-01-03
申请号：US09675801
申请日：2000-09-29
申请人： Jeffrey L. Rabe , Satish Acharya , Zohar Bogin , Serafin E. Garcia , David J. Harriman
发明人： Jeffrey L. Rabe , Satish Acharya , Zohar Bogin , Serafin E. Garcia , David J. Harriman
IPC分类号： G06F1/00
CPC分类号： G06F13/24
摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.
摘要翻译：一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。标记为最低优先级可重定向的中断根据任务优先级信息重定向。提供对XTPR事务的支持以更新XTPR寄存器。提供XTPR更新事务和重定向中断的优先顺序。

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