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1. 发明授权

US5444857A Method and apparatus for cycle tracking variable delay lines 失效
标题翻译：循环跟踪可变延迟线的方法和装置
公开(公告)号：US5444857A
公开(公告)日：1995-08-22
申请号：US60804
申请日：1993-05-12
申请人： Stephen T. Rowland
发明人： Stephen T. Rowland
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/4072
摘要： Peripheral components are interfaced to a computer system through cycle tracking variable delay lines. The computer system includes a system I/O containing, in part, a bus cycle tracking apparatus. The bus cycle tracking apparatus includes cycle tracking logic, a plurality of delay lines, leading and trailing multiplexors (MUXs) and a state MUX. The bus cycle tracking apparatus controls the asynchronous delay of an output reference signal. A plurality of leading and trailing timing reference signals are provided as inputs to the plurality of delay lines. The leading and trailing timing references are delayed by the delay lines a time specified in accordance with an AC timing specification. The bus cycle is tracked such that during a leading/idle state, the leading timing reference is selected as the output reference, and during a trailing state, the trailing reference is selected. The independent control of the output reference signal allows all bus cycle events to be controlled precisely and independently.
摘要翻译：外围组件通过循环跟踪可变延迟线与计算机系统连接。计算机系统包括部分地包含总线周期跟踪装置的系统I / O。总线周期跟踪装置包括循环跟踪逻辑，多个延迟线，前导和后置多路复用器（MUX）以及状态MUX。总线周期跟踪装置控制输出参考信号的异步延迟。提供多个前导和后期定时参考信号作为多个延迟线的输入。引导和结束定时参考根据AC定时规范指定的时间延迟延迟线。跟踪总线周期，使得在前导/空闲状态期间，选择引导定时参考作为输出参考，并且在拖尾状态期间，选择尾随参考。输出参考信号的独立控制允许所有总线周期事件被精确和独立地控制。

2. 发明授权

US5537664A Methods and apparatus for generating I/O recovery delays in a computer system 失效
标题翻译：在计算机系统中产生I / O恢复延迟的方法和装置
公开(公告)号：US5537664A
公开(公告)日：1996-07-16
申请号：US582664
申请日：1996-01-04
申请人： Stephen T. Rowland , Dahmane Dahmani
发明人： Stephen T. Rowland , Dahmane Dahmani
IPC分类号： G06F13/20
CPC分类号： G06F13/20
摘要： A computer system comprising programmable I/O recovery includes a device selection unit, programmable I/O recovery time registers, and a decrementer for specifying I/O recovery times for a plurality of I/O peripheral components. The programmable I/O recovery time registers contain time values, and the time values are programmable by the user of the computer system. The computer system interfaces the I/O peripheral components on an external bus through a plurality of bus cycle signals generated by cycle generation logic. For each I/O bus cycle on the external bus, the device selection unit identifies the I/O device involved in the I/O bus cycle. The device selection unit selects a time value from the programmable I/O recovery time registers corresponding to the I/O device identified, and loads the time value selected in the decrementer. Upon termination of the bus cycle, the device selection unit generates a cycle start signal to enable counting in the decrementer. The decrementer begins to count down from the time value loaded, and when the decrementer reaches a terminal count, a ready signal is generated. The ready signal enables the cycle generation logic to generate a successive bus cycle for the same I/O peripheral component.
摘要翻译：包括可编程I / O恢复的计算机系统包括设备选择单元，可编程I / O恢复时间寄存器和用于指定多个I / O外围组件的I / O恢复时间的减量器。可编程I / O恢复时间寄存器包含时间值，时间值可由计算机系统的用户编程。计算机系统通过由循环生成逻辑生成的多个总线周期信号将外部总线上的I / O外围部件连接起来。对于外部总线上的每个I / O总线周期，器件选择单元识别I / O总线周期中涉及的I / O设备。设备选择单元从所识别的I / O设备对应的可编程I / O恢复时间寄存器中选择时间值，并加载在减法器中选择的时间值。在总线周期结束时，设备选择单元产生一个周期开始信号，以使能在递减器中进行计数。减法器从加载的时间值开始倒计时，并且当减量器到达终端计数时，生成就绪信号。就绪信号使循环生成逻辑能够为相同的I / O外围组件生成连续的总线周期。

3. 发明授权

US5794070A Method and apparatus for fast DMA transfer on an industry standard architecture (ISA) bus 失效
标题翻译：用于工业标准架构（ISA）总线上快速DMA传输的方法和装置
公开(公告)号：US5794070A
公开(公告)日：1998-08-11
申请号：US730777
申请日：1996-10-16
申请人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
发明人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.
摘要翻译：计算机系统包括直接存储器访问（DMA）传送单元和通过外部总线耦合的多个DMA设备。 DMA传送单元为多个DMA设备实现DMA传输。 DMA传输单元包含DMA控制器，总线仲裁器和总线控制器。 DMA控制器和总线控制器产生一个两个时钟周期的DMA传输。为了实现双时钟周期DMA传输，请求的DMA设备与DMA控制器建立DMA传输，使得在第一时钟周期期间断言DACK＃信号。在第二个时钟周期内，DMA控制器设置存储器地址。在第三个时钟周期内，总线控制器转换外部总线上的命令信号。在断言命令信号时，有效数据在外部总线上被断言。对于需求和块模式操作，在两个时钟周期的DMA传输中执行额外的DMA传输。 DMA控制器和总线控制器也产生三个时钟周期的DMA传输。

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