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1. 发明授权

US06983339B1 Method and apparatus for processing interrupts of a bus 失效
标题翻译：一种用于处理总线中断的方法和装置
公开(公告)号：US06983339B1
公开(公告)日：2006-01-03
申请号：US09675801
申请日：2000-09-29
申请人： Jeffrey L. Rabe , Satish Acharya , Zohar Bogin , Serafin E. Garcia , David J. Harriman
发明人： Jeffrey L. Rabe , Satish Acharya , Zohar Bogin , Serafin E. Garcia , David J. Harriman
IPC分类号： G06F1/00
CPC分类号： G06F13/24
摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.
摘要翻译：一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。标记为最低优先级可重定向的中断根据任务优先级信息重定向。提供对XTPR事务的支持以更新XTPR寄存器。提供XTPR更新事务和重定向中断的优先顺序。

2. 发明授权

US06499085B2 Method and system for servicing cache line in response to partial cache line request 失效
公开(公告)号：US06499085B2
公开(公告)日：2002-12-24
申请号：US09752846
申请日：2000-12-29
申请人： Zohar Bogin , David J. Harriman , Zdzislaw A. Wirkus , Satish Acharya
发明人： Zohar Bogin , David J. Harriman , Zdzislaw A. Wirkus , Satish Acharya
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/0835
摘要： A system is described for servicing a full cache line in response to a partial cache line request. The system includes a storage to store at least one cache line, a hit/miss detector, and a data mover. The hit/miss detector receives a partial cache line read request from a requesting agent and dispatches a fetch request to a memory device to fetch a full cache line data that contains data requested in the partial cache line read request from the requesting agent. The data mover loads the storage with the full cache line data returned from the memory device and forwards a portion of the full cache line data requested by the requesting agent. If data specified in a subsequent partial cache line request from the requesting agent is contained within the full cache line data specified in the previously dispatched fetch request, the hit/miss detector will send a command to the data mover to forward another portion of the full cache line data stored in the storage to the requesting agent. In one embodiment, the system also includes a write combining logic to combine two or more consecutive write requests that meet defined conditions into a single write request.

3. 发明授权

US07082480B2 Managing bus transaction dependencies 失效
标题翻译：管理总线事务依赖关系
公开(公告)号：US07082480B2
公开(公告)日：2006-07-25
申请号：US10674944
申请日：2003-09-29
申请人： Zohar Bogin , Serafin E. Garcia
发明人： Zohar Bogin , Serafin E. Garcia
IPC分类号： G06F3/00
CPC分类号： G06F13/24 , G06F13/385
摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.
摘要翻译：在具有调度器和多个下行命令队列的计算机系统中防止死锁和活动锁的技术的组合。在一个实施例中，需要在所有受影响的下游命令队列中同时可用空间的广播事务变成延迟的事务，使得命令队列被保留，并且重试其他事务直到广播事务完成。在另一个实施例中，如果事务在预定时间内未完成，则使用拯救计时器推迟事务。在另一个实施例中，如果存在小于可用于该事务的预定量的下游缓冲区空间，则潜在地解决由可编程属性映射控制的存储空间的锁定事务被处理为延迟事务。

4. 发明授权

US06694390B1 Managing bus transaction dependencies 失效
公开(公告)号：US06694390B1
公开(公告)日：2004-02-17
申请号：US09659108
申请日：2000-09-11
申请人： Zohar Bogin , Serafin E. Garcia
发明人： Zohar Bogin , Serafin E. Garcia
IPC分类号： G06F300
CPC分类号： G06F13/24 , G06F13/385
摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

5. 发明授权

US06584526B1 Inserting bus inversion scheme in bus path without increased access latency 失效
标题翻译：在总线路径中插入总线反演方案，而不增加访问延迟
公开(公告)号：US06584526B1
公开(公告)日：2003-06-24
申请号：US09667049
申请日：2000-09-21
申请人： Zohar Bogin , Serafin E. Garcia , Steven J. Clohset
发明人： Zohar Bogin , Serafin E. Garcia , Steven J. Clohset
IPC分类号： G06F1338
CPC分类号： G06F11/10 , G06F13/4213 , G11C7/1078 , G11C7/1084
摘要： A technique to reduce accumulated latencies in bus transmission time when a bus inversion scheme is employed. The bus inversion scheme inverts all the data bits whenever more than one-half of the data bits are active, so that the bus never has more that one-half of the bits active during a data transfer. This minimizes the number of driver circuits that are actively driving the bus at any given time. Since it takes a certain amount to time to determine if more than one-half of the bits are active, this process can add to overall latency, or data transfer time on the bus. By placing the bus inversion function in parallel with another function that also contributes to bus latency, such as error correction code (ECC) calculation, only the more time-consuming of the two functions will increase bus latency.
摘要翻译：一种在采用总线反转方案时减少总线传输时间的累积延迟的技术。每当超过一半的数据位有效时，总线反相方案会反转所有数据位，这样在数据传输过程中，总线从不会有更多的一半位有效。这样可以最大限度地减少任何给定时间内积极驱动总线的驱动电路的数量。由于需要一定的时间来确定是否有超过一半的位是活动的，所以该过程可以增加总线上的总延迟或数据传输时间。通过将总线反转功能与还有助于总线等待时间（如纠错码（ECC））计算的另一个功能并行布置，只有更多的时间消耗这两个功能才能增加总线延迟。

6. 发明授权

US5655127A Method and apparatus for control of power consumption in a computer system 失效
标题翻译：用于控制计算机系统中功耗的方法和装置
公开(公告)号：US5655127A
公开(公告)日：1997-08-05
申请号：US612673
申请日：1996-03-08
申请人： Jeffrey L. Rabe , Zohar Bogin , Ajay V. Bhatt , James P. Kardach , Nilesh V. Shah
发明人： Jeffrey L. Rabe , Zohar Bogin , Ajay V. Bhatt , James P. Kardach , Nilesh V. Shah
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/3287 , Y02B60/1282 , Y02B60/32
摘要： A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.
摘要翻译：一种具有响应低功率模式和全功率工作模式的计算机系统。计算机系统包括功率消耗控制器，处理器和通信设备。功率消耗控制器响应于低功率事件或完全运行的事件而产生中断信号。功耗控制器还产生时钟控制信号。时钟控制信号在全功率工作模式期间被断言，并且在低功率操作模式期间另行断言第一持续时间并且断言第二持续时间。响应于断言的时钟控制信号，处理器将内部时钟信号抑制到处理器内的至少一个功能块，并且响应于无效时钟控制信号，处理器将内部时钟信号发送到内部时钟信号中的至少一个功能块处理器。通过在低功率操作模式期间将内部时钟信号发送到处理器内的至少一个功能块，处理器可以在低功率操作模式期间响应来自通信设备的通信信号。

7. 发明授权

US07343469B1 Remapping I/O device addresses into high memory using GART 有权
标题翻译：使用GART将I / O设备地址重新映射到高内存中
公开(公告)号：US07343469B1
公开(公告)日：2008-03-11
申请号：US09667050
申请日：2000-09-21
申请人： Zohar Bogin , Jeffrey L. Rabe
发明人： Zohar Bogin , Jeffrey L. Rabe
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F12/1027
摘要： An address translation apparatus and method that can convert a limited-range memory address from a peripheral device to an expanded-range memory address on the fly. The invention can expand the limited address capability of a peripheral bus, such as a PCI bus with a 4 GB address range, to a much larger address capability, such as a 64 GB address range. This conversion can be performed on the fly by hardware, so that no appreciable delay in transfer time is created. The conversion can be performed by adding features to a conventional graphics controller interface, thus minimizing the impact on circuit complexity and system cost.
摘要翻译：一种地址转换装置和方法，其可以将有限范围的存储器地址从外围设备转换为扩展存储器地址。本发明可以将诸如具有4GB地址范围的PCI总线等外围总线的有限地址能力扩展到更大的地址能力，例如64GB的地址范围。这种转换可以由硬件在飞行中执行，因此不会产生明显的传输时间延迟。可以通过向传统图形控制器接口添加特征来实现转换，从而最小化对电路复杂性和系统成本的影响。

8. 发明授权

US5551044A Method and apparatus for interrupt/SMI# ordering 失效
标题翻译：中断/ SMI＃排序的方法和装置
公开(公告)号：US5551044A
公开(公告)日：1996-08-27
申请号：US349065
申请日：1994-12-01
申请人： Nilesh V. Shah , Jeffrey L. Rabe , Zohar Bogin
发明人： Nilesh V. Shah , Jeffrey L. Rabe , Zohar Bogin
IPC分类号： G06F13/24 , G06F13/00
CPC分类号： G06F13/24
摘要： A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.
摘要翻译：用于控制计算机系统中的中断请求信号传输的电路。输入接收来自外部组件的中断请求。耦合到输入的第一电路响应于来自外部组件的中断请求而生成信号。信号使处理器切换到完全运行模式。耦合到输入的第二电路响应于来自外部组件的中断请求，向处理器生成中断请求信号。耦合到第二电路的信号处理电路抑制中断请求信号到处理器的传输，直到信号被发送到处理器。

9. 发明授权

US07610611B2 Prioritized address decoder 有权
标题翻译：优先地址解码器
公开(公告)号：US07610611B2
公开(公告)日：2009-10-27
申请号：US10666077
申请日：2003-09-19
申请人： Douglas R. Moran , Satish Acharya , Zohar Bogin , Sean G. Galloway
发明人： Douglas R. Moran , Satish Acharya , Zohar Bogin , Sean G. Galloway
IPC分类号： G06F7/04 , G06F17/30 , G06K9/00 , H04L9/32
CPC分类号： G06F12/1441
摘要： A prioritized address decoder has been disclosed. One embodiment of the prioritized address decoder includes a first comparator to compare a destination device address of data with a first address range associated with a first device and a second comparator coupled to the first comparator to compare the destination device address with a second address range associated with a second device, wherein the data is sent to the second device in response to a first output of the first comparator and a second output of the second comparator.
摘要翻译：已经公开了优先地址解码器。优先地址解码器的一个实施例包括第一比较器，用于将数据的目的地设备地址与与第一设备相关联的第一地址范围和耦合到第一比较器的第二比较器进行比较，以将目的地设备地址与相关联的第二地址范围进行比较利用第二设备，其中响应于第一比较器的第一输出和第二比较器的第二输出将数据发送到第二设备。

10. 发明授权

US07114087B2 Method to detect a temperature change by a thermal monitor and compensating for process, voltage, temperature effects caused by the temperature change 有权
标题翻译：通过热监测器检测温度变化的方法，并补偿由温度变化引起的过程，电压，温度影响
公开(公告)号：US07114087B2
公开(公告)日：2006-09-26
申请号：US10446549
申请日：2003-05-27
申请人： Christine Watnik , Zohar Bogin , Buderya “Satish” Acharya , Romesh Trivedi
发明人： Christine Watnik , Zohar Bogin , Buderya “Satish” Acharya , Romesh Trivedi
IPC分类号： G06F1/26
CPC分类号： G06F1/206
摘要： According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU), a bus coupled to the CPU and a chipset coupled to the bus. The chipset includes compensation circuitry to compensate for process, voltage and temperature (PVT) effects attributed to a voltage change on the bus.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括中央处理单元（CPU），耦合到CPU的总线和耦合到总线的芯片组。该芯片组包括补偿电路，以补偿归因于总线上的电压变化的过程，电压和温度（PVT）效应。

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