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1. 发明申请

US20090172331A1 Securing content for playback 审中-公开
标题翻译：保护播放内容
公开(公告)号：US20090172331A1
公开(公告)日：2009-07-02
申请号：US12006282
申请日：2007-12-31
申请人： Balaji Vembu , Aditya Sreenivas , Wishwesh Gandhi , Sathyamurthi Sadhasivan , Gary Graunke , Scott Janus , Murali Ramadoss
发明人： Balaji Vembu , Aditya Sreenivas , Wishwesh Gandhi , Sathyamurthi Sadhasivan , Gary Graunke , Scott Janus , Murali Ramadoss
IPC分类号： G06F21/00
CPC分类号： G06F21/84 , G06F21/10 , G06F21/74
摘要： A graphics engine may include a decryption device, a renderer, and a sprite or overlay engine, all connected to a display. A memory may have a protected and non-protected portions in one embodiment. An application may store encrypted content on the non-protected portion of said memory. The decryption device may access the encrypted material, decrypt the material, and provide it to the renderer engine of a graphics engine. The graphics engine may then process the decrypted material using the protected portion of the memory. Only graphics devices can access the protected portion of the memory in at least one mode, preventing access by outside sources. In addition, the protected memory may be stolen memory that is not identified to the operating system, making that stolen memory inaccessible to applications running on the operating system.
摘要翻译：图形引擎可以包括全部连接到显示器的解密设备，渲染器和子画面或覆盖引擎。在一个实施例中，存储器可以具有受保护和非保护部分。应用可以将加密的内容存储在所述存储器的非保护部分上。解密设备可以访问加密的材料，解密材料，并将其提供给图形引擎的渲染器引擎。然后，图形引擎可以使用存储器的受保护部分来处理解密的材料。只有图形设备才能以至少一种模式访问存储器的受保护部分，从而防止外部源的访问。此外，受保护的存储器可能是未被识别到操作系统的被盗存储器，使得被盗的存储器不能在操作系统上运行的应用程序访问。

2. 发明授权

US07321369B2 Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device 有权
标题翻译：用于在图形控制器设备上同步多个异步客户端队列的处理的方法和装置
公开(公告)号：US07321369B2
公开(公告)日：2008-01-22
申请号：US10232285
申请日：2002-08-30
申请人： David A. Wyatt , Aditya Sreenivas
发明人： David A. Wyatt , Aditya Sreenivas
IPC分类号： G09G5/36 , G06F1/00
CPC分类号： G06F9/3851 , G06F9/3879 , G06T15/005
摘要： An apparatus and method are disclosed for synchronization of command processing from multiple command queues. Various embodiments employ a condition code register that indicates which queues should have processing suspended until a specified event condition occurs. Upon satisfaction of the specified condition, processing of commands from the suspended queue is resumed.
摘要翻译：公开了用于从多个命令队列同步命令处理的装置和方法。各种实施例使用条件码寄存器，其指示哪些队列应该具有暂停的处理，直到发生指定的事件条件。满足指定条件后，恢复从挂起的队列处理命令。

3. 发明申请

US20070188508A1 Optimized memory addressing 有权
公开(公告)号：US20070188508A1
公开(公告)日：2007-08-16
申请号：US11784342
申请日：2007-04-06
申请人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
发明人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
IPC分类号： G09G5/399
CPC分类号： G06F13/1684
摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

4. 发明授权

US06792516B2 Memory arbiter with intelligent page gathering logic 失效
标题翻译：具有智能页面采集逻辑的内存仲裁器
公开(公告)号：US06792516B2
公开(公告)日：2004-09-14
申请号：US10033440
申请日：2001-12-28
申请人： Josh B. Mastronarde , Aditya Sreenivas , Thomas A. Piazza
发明人： Josh B. Mastronarde , Aditya Sreenivas , Thomas A. Piazza
IPC分类号： G06F1200
CPC分类号： G06F13/161 , G06F13/18
摘要： Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.
摘要翻译：本发明的实施例提供了一种用于将芯片组和图形业务引导到系统存储器的存储器仲裁器。页面一致性和优先级用于优化内存带宽利用率，并保证等时显示请求的延迟。仲裁器还包含一种防止CPU请求饥饿较低优先级请求的机制。因此，存储器仲裁器提供了一种简单易于验证的架构，防止CPU不利地挨饿低优先级代理，并利用宽限期和存储器页面检测来优化仲裁交换机，从而增加内存带宽利用率。

5. 发明授权

US06538650B1 Efficient TLB entry management for the render operands residing in the tiled memory 有权
标题翻译：对于驻留在平铺内存中的渲染操作数的高效TLB条目管理
公开(公告)号：US06538650B1
公开(公告)日：2003-03-25
申请号：US09480833
申请日：2000-01-10
申请人： Surti B. Prasoonkumar , Aditya Sreenivas
发明人： Surti B. Prasoonkumar , Aditya Sreenivas
IPC分类号： G06T1700
CPC分类号： G06T15/005 , G06F12/1027 , G06F2212/654
摘要： A method and apparatus for efficient translation lookaside buffer (“TLB”) management of three-dimensional surfaces is disclosed. A three-dimensional surface is represented as a square pixel surface. The square-surface representation is stored in a single entry of the TLB.
摘要翻译：公开了一种用于三维表面的有效翻译后备缓冲（“TLB”）管理的方法和装置。三维表面被表示为正方形像素表面。正方形表示形式存储在TLB的单个条目中。

6. 发明授权

US07173627B2 Apparatus, method and system with a graphics-rendering engine having a graphics context manager 有权
标题翻译：具有图形渲染引擎的装置，方法和系统具有图形上下文管理器
公开(公告)号：US07173627B2
公开(公告)日：2007-02-06
申请号：US09895777
申请日：2001-06-29
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
IPC分类号： G06F15/00 , G06F9/46
CPC分类号： G06F9/463
摘要： A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.
摘要翻译：一种同时呈现独立图像以在一个或多个显示设备上显示的方法，装置和系统。在一个实施例中，图形呈现引擎同时呈现独立图像以在多个显示设备上显示。图形上下文管理器存储在第一存储器区域中，并且从第一存储器区域恢复描述与第一独立图像相关联的第一渲染上下文的信息。图形上下文管理器存储在第二存储器区域中，并且从第二存储器区域恢复描述与第二独立图像相关联的第二渲染上下文的信息。

7. 发明授权

US07103730B2 Method, system, and apparatus for reducing power consumption of a memory 有权
标题翻译：用于降低存储器功耗的方法，系统和装置
公开(公告)号：US07103730B2
公开(公告)日：2006-09-05
申请号：US10119864
申请日：2002-04-09
申请人： Alankar Saxena , Aditya Sreenivas
发明人： Alankar Saxena , Aditya Sreenivas
IPC分类号： G06F12/00 , G06F1/32
CPC分类号： G06F1/3225 , G06F1/3275 , G06F12/0215 , G06F12/123 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a LRU status of the rows in an active mode.
摘要翻译：至少部分地基于活动模式中的行的LRU状态来主动地断言CKE引脚来减少存储器的功耗的方法，系统和装置。

8. 发明授权

US07035984B2 Memory arbiter with grace and ceiling periods and intelligent page gathering logic 失效
公开(公告)号：US07035984B2
公开(公告)日：2006-04-25
申请号：US10038941
申请日：2001-12-31
申请人： Josh B. Mastronarde , Aditya Sreenivas , Thomas A. Piazza
发明人： Josh B. Mastronarde , Aditya Sreenivas , Thomas A. Piazza
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1642
摘要： Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

9. 发明授权

US06999091B2 Dual memory channel interleaving for graphics and video 有权
标题翻译：用于图形和视频的双存储器通道交织
公开(公告)号：US06999091B2
公开(公告)日：2006-02-14
申请号：US10033439
申请日：2001-12-28
申请人： Alankar Saxena , Aditya Sreenivas , Tom A. Piazza
发明人： Alankar Saxena , Aditya Sreenivas , Tom A. Piazza
IPC分类号： G06F12/02
CPC分类号： G09G5/39 , G09G2360/122 , G09G2360/125 , H04N19/423 , H04N19/61
摘要： Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.
摘要翻译：本发明的实施例提供了一种用于将平铺的存储器表面最佳地映射到两个存储器通道的方法和装置，以交错的方式操作，使两个通道的存储器效率最大化，同时保持期望的访问粒度。特别地，输入请求地址用于基于瓦片和请求参数来生成用于存储器通道的存储器地址。存储器控制器以这样的格式将该组平铺数据存储在存储器中，使得所选择的拼接数据集合被存储在存储器的交替通道中，使得数据块可以同时访问，而不是依次访问。因此，如果存储器控制器从诸如图形引擎的源接收到数据块，则存储器控制器将存储器中的单个存储器中的数据块的部分存储在存储器中，从而被分割，使得其可经由存储器的备用通道与此同时。

10. 发明申请

US20050283602A1 Apparatus and method for protected execution of graphics applications 审中-公开
标题翻译：保护执行图形应用的装置和方法
公开(公告)号：US20050283602A1
公开(公告)日：2005-12-22
申请号：US10873803
申请日：2004-06-21
申请人： Balaji Vembu , Clifford Hall , Aditya Sreenivas
发明人： Balaji Vembu , Clifford Hall , Aditya Sreenivas
IPC分类号： G06F12/10 , G06F12/14 , G06F21/00 , H04L9/00
CPC分类号： G06F21/53 , G06F12/1036 , G06F12/1081 , G06F12/109 , G06F12/145
摘要： A method and apparatus for protected execution of graphics are described. In one embodiment, the method includes the formation of a translation table for a trusted application. In one embodiment, the translation table is formed according to one or more protected pages assigned to the trusted application in response to a protected page request from the trusted application. During execution of the trusted application, a virtual address space of the trusted application is translated to the one or more protected pages assigned to the trusted application. In one embodiment, the translation is performed according to the translation table assigned to the trusted application. Accordingly, by assigning a unique translation table to each trusted application, the various trusted applications may execute within the platform without generating an access into another application's physical address space. Other embodiments are described and claimed.
摘要翻译：描述用于保护执行图形的方法和装置。在一个实施例中，该方法包括形成可信应用的转换表。在一个实施例中，响应于受信任应用的受保护的页面请求，根据分配给受信任应用的一个或多个受保护页形成翻译表。在可信应用的执行期间，可信应用的虚拟地址空间被转换为分配给可信应用的一个或多个受保护的页面。在一个实施例中，根据分配给可信应用的转换表来执行翻译。因此，通过为每个可信应用分配唯一的转换表，各种可信应用可以在平台内执行，而不产生对另一个应用的物理地址空间的访问。描述和要求保护其他实施例。

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