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1. 发明授权

US5596729A First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus 失效
标题翻译：第一仲裁器耦合到第一总线，接收来自耦合到第二总线并由所述第二总线上的第二仲裁器控制的设备的请求
公开(公告)号：US5596729A
公开(公告)日：1997-01-21
申请号：US398366
申请日：1995-03-03
申请人： Robert A. Lester , Jeff W. Wolford
发明人： Robert A. Lester , Jeff W. Wolford
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/36
摘要： An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.
摘要翻译：一种改进的仲裁方案，包括用于仲裁访问PCI总线和ISA总线的多仲裁器。 PCI仲裁器控制各种总线主机访问PCI总线，包括CPU /主存储器子系统，各种其他PCI总线主机，增强型DMA或EDMA控制器以及兼容8237的DMA控制器。 PCI仲裁器利用修改的LRU仲裁方案。此外，SD仲裁器存在仲裁访问ISA总线的数据部分（SD）。可以请求SD总线的各种设备包括EDMA控制器，PCI-ISA操作中的PCI主机，DMA控制器，ISA总线主机和刷新控制器。 SD仲裁器将最高优先级分配给PCI总线，其次是刷新控制器，EDMA控制器和DMA控制器或ISA总线主机。 DMA控制器包括用于在其通道之间进行仲裁的仲裁器。 DMA仲裁器还包括确保DMA控制器或ISA总线主机在一个仲裁周期之后放弃对ISA总线的控制的逻辑。

2. 发明授权

US06272580B1 Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system 有权
标题翻译：一种用于在多级仲裁系统内动态地将较低级总线主机升级到上级总线主机的装置和方法
公开(公告)号：US06272580B1
公开(公告)日：2001-08-07
申请号：US09268825
申请日：1999-03-16
申请人： Jeff Stevens , Robert A. Lester , Phillip M. Jones , Jeff W. Wolford , Peter Lee
发明人： Jeff Stevens , Robert A. Lester , Phillip M. Jones , Jeff W. Wolford , Peter Lee
IPC分类号： G06F13362
CPC分类号： G06F13/362
摘要： A computer system, bus interface unit, and method are provided to allocate requests to a shared bus within the computer system. The bus interface unit includes an arbiter which employs a multi-level, round-robin arbitration protocol. Configuration registers are programmed during boot-up of the computer system by assigning a subset of peripheral devices, bus agents, requesters, or bus masters to either a high priority ring or a low priority ring, if two levels of arbitration are used. The status of a low priority device can be elevated to equal priority with a high priority device by assigning the low priority device to a high priority port within the high priority ring if certain circumstances occur. Namely, if data transfers to or from the low priority device are terminated, then the low priority device will be promoted to a high priority device so that it need not wait until after the all high priority device requests have been polled. Instead, the elevated low priority device is placed on the same level of priority as the high priority devices so that its request can be readily serviced and the transaction completed during a data transfer retry operation.
摘要翻译：提供计算机系统，总线接口单元和方法以将计算机系统中的共享总线分配请求。总线接口单元包括采用多级循环仲裁协议的仲裁器。如果使用两级仲裁，配置寄存器在计算机系统引导期间被编程，通过将外设，总线代理，请求者或总线主机的子集分配到高优先级环或低优先级环。如果发生某些情况，则可以通过将低优先级设备分配给高优先级环中的高优先级端口，将低优先级设备的状态提升为与高优先级设备相等的优先级。也就是说，如果到低优先级设备的数据传输结束，则低优先级设备将被提升为高优先级设备，使得它不需要等到所有高优先级设备请求被轮询之后。相反，升高的低优先级设备被放置在与高优先级设备相同的优先级上，使得其请求可以容易地被服务并且在数据传输重试操作期间完成事务。

3. 发明授权

US5603050A Direct memory access controller having programmable timing 失效
公开(公告)号：US5603050A
公开(公告)日：1997-02-11
申请号：US398358
申请日：1995-03-03
申请人： Jeff W. Wolford , Robert A. Lester
发明人： Jeff W. Wolford , Robert A. Lester
IPC分类号： G06F13/28 , G06F13/30 , G06F13/362 , G06F13/00
CPC分类号： G06F13/30 , G06F13/28 , G06F13/287 , G06F13/3625
摘要： An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.

4. 发明授权

US5463753A Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller 失效
标题翻译：通过将主机总线许可信号延迟到高速缓存控制器来减少高速缓存控制器的非窥探窗口的方法和装置
公开(公告)号：US5463753A
公开(公告)日：1995-10-31
申请号：US955501
申请日：1992-10-02
申请人： Walter G. Fry , Jeff W. Wolford
发明人： Walter G. Fry , Jeff W. Wolford
IPC分类号： G06F12/08 , G06F13/36 , G06F13/14
CPC分类号： G06F13/36 , G06F12/0831
摘要： A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.
摘要翻译：一种在某些操作期间减少高速缓存控制器的非窥探窗口以增加主机总线效率的方法和装置。高速缓存控制器需要总线授权信号来执行周期，并且在提供总线授权信号直到循环完成之后才能窥探周期。缓存接口逻辑监控缓存控制器的周期，这些周期需要扩展总线或本地I / O总线。当检测到这样的周期时，设备开始周期，并且不向总线授权信号断言到高速缓存控制器。因此，高速缓存控制器认为该周期尚未开始，因此能够执行其他操作，例如窥探其他主机总线周期。在此期间，循环执行。当读取数据返回或写数据到达其目的地时，接口逻辑在适当的时间向缓存控制器提供总线授权周期。通过以这种方式延迟总线授权信号，减少非窥视窗口。

5. 发明授权

US5434997A Method and apparatus for testing and debugging a tightly coupled mirrored processing system 失效
标题翻译：用于测试和调试紧耦合镜像处理系统的方法和装置
公开(公告)号：US5434997A
公开(公告)日：1995-07-18
申请号：US955980
申请日：1992-10-02
申请人： John A. Landry , Jeff W. Wolford , Walter G. Fry , Roger E. Tipley
发明人： John A. Landry , Jeff W. Wolford , Walter G. Fry , Roger E. Tipley
IPC分类号： G06F11/16 , G06F11/00 , G06F17/30
CPC分类号： G06F11/1637 , G06F11/1679
摘要： A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.
摘要翻译：一种用于在计算机系统中操作紧耦合的镜像处理器的方法和装置。多个CPU板耦合到通常称为主机总线的处理器/存储器总线。每个CPU板包括一个处理器以及各个处理器本地的各种端口，定时器和中断控制器逻辑。一个或多个CPU板上的处理器被指定为主处理器，其余CPU板上的处理器被指定为镜像或从属处理器。主处理器具有对主机总线的完全访问和用于读和写周期的第二复用总线，而从处理器被阻止写入任何总线。从处理器将写入数据和各种控制信号与其相应的主处理器产生的差异进行比较。该系统包括中断控制器同步逻辑，以同步中断请求以及定时器同步逻辑，以同步每个主CPU和从CPU的定时器，以保证主CPU和从CPU处于锁定状态。

6. 发明授权

US06226700B1 Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices 失效
标题翻译：具有桥逻辑的计算机系统，包括内部模块化扩展总线和用于内部主设备的公共主接口
公开(公告)号：US06226700B1
公开(公告)日：2001-05-01
申请号：US09042173
申请日：1998-03-13
申请人： Shaun Wandler , Jeffrey C. Stevens , Jeff W. Wolford , Robert Woods , Danny Higby , Russ Wunderlich , Todd Deschepper , Jeffrey T. Wilson
发明人： Shaun Wandler , Jeffrey C. Stevens , Jeff W. Wolford , Robert Woods , Danny Higby , Russ Wunderlich , Todd Deschepper , Jeffrey T. Wilson
IPC分类号： G06F1340
CPC分类号： G06F13/4045
摘要： A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus. The master interface then is responsible for understanding the protocol of the expansion bus and converting the IMAX master bus signals to signals compatible with the expansion bus. In addition, a dedicated target IMAX bus may also be provided for coupling internal targets within the South bridge to masters on the expansion bus through a common expansion target interface.
摘要翻译：计算机系统包括CPU和由北桥逻辑单元耦合到诸如PCI总线的扩展总线的存储器件。南桥逻辑连接到扩展总线，并将各种辅助总线和外围设备耦合到扩展总线。南桥逻辑包括设计用于在扩展总线上运行主站周期的内部控制设备或主设备。主器件通过公共扩展主接口耦合到扩展总线，该接口代表主器件在扩展总线上执行主器件周期。南桥还包括将内部主设备连接到公共主接口的内部模块化主扩展总线。内部模块化主扩展总线允许主器件通过了解由内部模块化主扩展（IMAX）总线表示的标准化信号组，将主周期运行到任何扩展总线。然后，主接口负责了解扩展总线的协议，并将IMAX主总线信号转换为与扩展总线兼容的信号。此外，还可以提供专用目标IMAX总线，用于通过公共扩展目标接口将南桥内的内部目标耦合到扩展总线上的主设备。

7. 发明授权

US5802318A Universal serial bus keyboard system 失效
标题翻译：通用串行总线键盘系统
公开(公告)号：US5802318A
公开(公告)日：1998-09-01
申请号：US506884
申请日：1995-07-25
申请人： David E. Murray , David R. Wooten , Randall L. Hess , Christopher C. Wanner , Jeff W. Wolford
发明人： David E. Murray , David R. Wooten , Randall L. Hess , Christopher C. Wanner , Jeff W. Wolford
IPC分类号： G06F3/023 , G06F3/038 , G06F9/445 , G06F13/10 , G06F13/12 , G06F3/00 , G06F9/46
CPC分类号： G06F3/038 , G06F13/105 , G06F13/126 , G06F3/023 , G06F9/4411
摘要： A keyboard system according to the present invention includes a serial bus host controller coupled to a serial bus keyboard. The keyboard includes both keyboard scan logic and scan code conversion logic for passing to the host controller over the serial bus. The host controller includes circuitry for processing the data between the serial bus and a host bus. The host controller further includes 8042 emulation logic for providing a hardware compatible interface to the keyboard controller. The 8042 emulation logic also includes circuitry for communicating over the serial bus during times when the serial bus has not yet been initialized.
摘要翻译：根据本发明的键盘系统包括耦合到串行总线键盘的串行总线主机控制器。键盘包括键盘扫描逻辑和扫描码转换逻辑，用于通过串行总线传送到主机控制器。主机控制器包括用于处理串行总线和主机总线之间的数据的电路。主机控制器还包括用于向键盘控制器提供硬件兼容接口的8042仿真逻辑。 8042仿真逻辑还包括在串行总线尚未初始化的时间内通过串行总线通信的电路。

8. 发明授权

US5353415A Method and apparatus for concurrency of bus operations 失效
标题翻译：总线运行并发的方法和装置
公开(公告)号：US5353415A
公开(公告)日：1994-10-04
申请号：US955477
申请日：1992-10-02
申请人： Jeff W. Wolford , Walter G. Fry
发明人： Jeff W. Wolford , Walter G. Fry
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.
摘要翻译：一种在主机总线，扩展总线和本地I / O总线上执行并行操作的方法和装置，以及连接处理器和缓存系统的处理器总线，以提高计算机系统的效率。多个CPU板耦合到主机总线，主机总线又通过总线控制器耦合到扩展总线。每个CPU板包括连接到包括高速缓存控制器和高速缓冲存储器的高速缓存系统的处理器。缓存系统通过由缓存接口逻辑控制的地址和数据缓冲器与主机总线进行接口。包括各种端口，定时器和中断控制器逻辑的分布式系统外设（DSP）逻辑由本地I / O总线耦合到高速缓存系统，数据缓冲器和高速缓存接口逻辑。计算机系统支持并行操作的各个领域，包括并发本地I / O周期，主机总线侦听周期和CPU请求以及带有主机总线周期的并发扩展总线读取。

9. 发明申请

US20110265191A1 SYSTEM AND METHOD FOR PLACING AN ELECTRONIC APPARATUS INTO A PROTECTED STATE IN RESPONSE TO ENVIRONMENTAL DATA 有权
标题翻译：将电子设备放置在保护状态以响应环境数据的系统和方法
公开(公告)号：US20110265191A1
公开(公告)日：2011-10-27
申请号：US12765041
申请日：2010-04-22
申请人： Leonard E. Russo , Walter A. Gaspard , Jeff W. Wolford , Richard J. Tomaszewski , Robert C. Elliott
发明人： Leonard E. Russo , Walter A. Gaspard , Jeff W. Wolford , Richard J. Tomaszewski , Robert C. Elliott
IPC分类号： G06F21/02
CPC分类号： G06F21/78 , G06F21/6209 , G06F21/74 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , G06F2221/2147 , G06F2221/2149
摘要： A system and method is disclosed for placing an electronic apparatus into a protected state in response to environmental data. The method discloses: receiving a set of environmental data applicable to an electronic apparatus; generating an environmental status applicable to the electronic apparatus based-on the environmental data; and placing the electronic apparatus into a protected state based-on the environmental status. The system discloses an environment characterization module which receives a set of environmental data applicable to an electronic apparatus, and generates an environmental status applicable to the electronic apparatus based-on the environmental data; and an apparatus protection module which places the electronic apparatus into a protected state based-on the environmental status.
摘要翻译：公开了一种用于响应于环境数据将电子设备置于受保护状态的系统和方法。该方法公开：接收适用于电子设备的一组环境数据; 基于环境数据产生适用于电子设备的环境状态; 并且基于环境状态将电子设备置于受保护状态。该系统公开了一种环境表征模块，其接收可应用于电子设备的一组环境数据，并且基于环境数据生成可应用于电子设备的环境状态; 以及基于环境状态将电子设备置于受保护状态的设备保护模块。

10. 发明授权

US5884095A Direct memory access controller having programmable timing 失效
标题翻译：具有可编程时序的直接存储器存取控制器
公开(公告)号：US5884095A
公开(公告)日：1999-03-16
申请号：US815731
申请日：1997-03-12
申请人： Jeff W. Wolford , Robert Allan Lester
发明人： Jeff W. Wolford , Robert Allan Lester
IPC分类号： G06F13/28 , G06F13/30 , G06F13/362
CPC分类号： G06F13/30 , G06F13/28 , G06F13/287 , G06F13/3625
摘要： An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.
摘要翻译：改进的DMA控制器，具有可编程数据传输定时。总循环时间不仅可编程，而且循环的有效和无效周期也可编程。一个有效的定时寄存器和一个无效的定时寄存器与倒计时定时器结合使用，以确定数据传输周期的有效和无效周期。有效时间段在有效阶段加载到定时器中，活动阶段的结束由定时器超时指示。接下来，将非活动时间段加载到定时器中，其类似地超时以指示数据传送周期的非活动阶段的结束。

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