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1. 发明授权

US07395380B2 Selective snooping by snoop masters to locate updated data 失效
标题翻译：通过窥探大师进行选择性窥探以查找更新的数据
公开(公告)号：US07395380B2
公开(公告)日：2008-07-01
申请号：US10393116
申请日：2003-03-20
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro.Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
摘要翻译：一种用于窥探连接到总线宏的多个窥探主机的高速缓冲存储器的方法和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但是小于所有高速缓存存储器可以具有由始发侦听器请求的数据主站，并且其中非起始侦听主控器中的所需数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。只有那些可能具有请求的数据的非始发侦听主机才被查询。所有被查询的非始发侦听主人都回复。如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

2. 发明授权

US07685373B2 Selective snooping by snoop masters to locate updated data 失效
标题翻译：通过窥探大师进行选择性窥探以查找更新的数据
公开(公告)号：US07685373B2
公开(公告)日：2010-03-23
申请号：US11970599
申请日：2008-01-08
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A system and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has a cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in an non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
摘要翻译：一种用于窥探连接到总线宏的多个窥探主机的高速缓存存储器的系统和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但不到全部高速缓冲存储器可具有始发请求的数据窥探主机，其中在非始发侦听主机中所需的数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。只有那些可能具有请求的数据的非始发侦听主机才被查询。所有被查询的非始发侦听主人都回复。如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

3. 发明授权

US06976132B2 Reducing latency of a snoop tenure 失效
标题翻译：减少窥探权限的延迟
公开(公告)号：US06976132B2
公开(公告)日：2005-12-13
申请号：US10249304
申请日：2003-03-28
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method and system for reducing latency of a snoop tenure. A bus macro may receive a snoopable transfer request. The bus macro may determine which snoop controllers in a system will participate in the snoop transaction. The bus macro may then identify which participating snoop controllers are passive. Passive snoop controllers are snoop controllers associated with cache memories with cache lines only in the shared or invalid states of the MESI protocol. The snoop request may then be completed by the bus macro without waiting to receive responses from the passive participating snoop controllers. By not waiting for responses from passive snoop controllers, the bus macro may be able to complete the snoop request in a shorter amount of time thereby reducing the latency of the snoop tenure and improving performance of the system bus.
摘要翻译：一种减少窥探权限延迟的方法和系统。总线宏可以接收可窥探的传输请求。总线宏可以确定系统中哪个侦听控制器将参与侦听事务。总线宏可能会识别哪些参与侦听控制器是被动的。被动侦听控制器是与高速缓存存储器相关联的监听控制器，其高速缓存线仅在MESI协议的共享或无效状态。然后可以由总线宏完成窥探请求，而不等待从被动参与侦听控制器接收响应。通过不等待来自被动侦听控制器的响应，总线宏可能能够在更短的时间内完成窥探请求，从而减少了窥探任务的延迟并提高了系统总线的性能。

4. 发明授权

US07089376B2 Reducing snoop response time for snoopers without copies of requested data via snoop filtering 失效
标题翻译：通过窥探过滤减少窥探者的窥探响应时间，而无需复制所请求的数据
公开(公告)号：US07089376B2
公开(公告)日：2006-08-08
申请号：US10442485
申请日：2003-05-21
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering device and method parse a snoop request issued by one of the plurality of snooping masters and return an Immediate Response if parsing indicates the requested data cannot possibly be contained in a responding snooping master. If parsing indicates otherwise the at least one plurality of snoop masters searches its resources and returns the requested data if marked updated.
摘要翻译：在具有耦合到总线宏的多个窥探主器件的系统中，在多个窥探主机中的至少一个中提供窥探过滤装置和方法。窥探过滤设备和方法解析多个窥探主机之一发出的窥探请求，并且如果解析指示所请求的数据不可能包含在响应侦听主机中，则返回立即响应。如果解析指示，否则至少一个多个窥探大师搜索其资源并且如果标记更新则返回所请求的数据。

5. 发明授权

US06970962B2 Transfer request pipeline throttling 失效
标题翻译：传输请求管道节流
公开(公告)号：US06970962B2
公开(公告)日：2005-11-29
申请号：US10440778
申请日：2003-05-19
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/08 , G06F13/00 , G06F13/42
CPC分类号： G06F12/0831 , G06F13/4217 , G06F2213/0038 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.
摘要翻译：一种用于在计算机系统内互连设备的流水线总线接口宏的方法和系统。该系统和方法利用流水线深度信号，其指示可以由发送设备发送并由接收设备在接收设备确认传送请求之前由接收设备发送的离散传送请求的数量N。可以动态地修改流水线深度信号，使得接收设备在已经做出一个或多个未确认的请求时减小或增加流水线深度。动态修改可以响应许多因素而发生，例如系统功耗的瞬时降低，总线接口性能指示器，接收设备性能指标或系统性能指标。

6. 发明授权

US07093058B2 Single request data transfer regardless of size and alignment 失效
标题翻译：单个请求数据传输，无论大小和对齐方式
公开(公告)号：US07093058B2
公开(公告)日：2006-08-15
申请号：US11246427
申请日：2005-10-07
申请人： Victor R. Angsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
发明人： Victor R. Angsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
IPC分类号： G06F13/40 , H04L12/56
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer. In terms of multiple beat transfers, the number of data transfer requests are reduced, which reduces the amount of switching, bus arbitration and power consumption required. In addition, the invention allows byte enable signals to be used for subsequent data transfer requests prior to the completion of the initial data transfer, which reduces power consumption and allows for pipelining of data transfer requests.
摘要翻译：公开了一种方法，计算机系统和一组信号，允许通过总线在使用单个传送请求的主机和从机之间进行数据传输的通信，而不管传送大小和对准。本发明提供了三个传送限定符信号，包括：包括数据传送的起始字节地址的第一信号; 第二信号，包括数据传输数据的大小; 以及第三信号，包括在数据传输的最后数据跳动期间所需的每个字节的字节使能。本发明可用于单节拍或多节拍，对齐或未对齐的数据传送。三个传输限定符信号的使用为从机提供了在传输开始时传输的数据跳数以及起始和结束数据跳数的对齐。因此，从机不需要计算它将传输的字节数。在多节拍传输方面，减少了数据传输请求的数量，从而减少了切换量，总线仲裁和所需的功耗。此外，本发明允许在完成初始数据传输之前将字节使能信号用于随后的数据传输请求，这降低了功耗并且允许数据传送请求的流水线化。

7. 发明授权

US06993619B2 Single request data transfer regardless of size and alignment 失效
公开(公告)号：US06993619B2
公开(公告)日：2006-01-31
申请号：US10249302
申请日：2003-03-28
申请人： Victor E. Augsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
发明人： Victor E. Augsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
IPC分类号： G06F13/40 , H04L12/56
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer. In terms of multiple beat transfers, the number of data transfer requests are reduced, which reduces the amount of switching, bus arbitration and power consumption required. In addition, the invention allows byte enable signals to be used for subsequent data transfer requests prior to the completion of the initial data transfer, which reduces power consumption and allows for pipelining of data transfer requests.

8. 发明授权

US07065595B2 Method and apparatus for bus access allocation 失效
标题翻译：总线接入分配的方法和装置
公开(公告)号：US07065595B2
公开(公告)日：2006-06-20
申请号：US10249271
申请日：2003-03-27
申请人： Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann
发明人： Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann
IPC分类号： G06F13/362
CPC分类号： G06F13/3625
摘要： A method for granting access to a bus is disclosed where a fair arbitration is modified to account for varying conditions. Each bus master (BM) is assigned a Grant Balance Factor value (hereafter GBF) that corresponds to a desired bandwidth from the bus. Arbitration gives priority BMs with a GBF greater than zero in a stratified protocol where requesting BMs with the same highest priority are granted access first. The GBF of a BM is decremented each time an access is granted. Requesting BMs with a GBF equal to zero are fairly arbitrated when there are no requesting BMs with GBFs greater than zero wherein they receive equal access using a frozen arbiter status. The bus access time may be partitioned into bus intervals (BIs) each comprising N clock cycles. BIs and GBFs may be modified to guarantee balanced access over multiple BIs in response to error conditions or interrupts.
摘要翻译：公开了一种允许访问总线的方法，其中公平仲裁被修改以解决变化的条件。为每个总线主机（BM）分配一个与总线所需带宽对应的授权平衡因子值（以下称为GBF）。仲裁在分层协议中给予GBF大于零的优先级BM，其中首先授予具有相同最高优先权的BM。每次授予访问权限时，BM的GBF都将递减。当没有请求具有大于零的GBF的BM时，请求具有等于零的GBF的BM被相当地仲裁，其中它们使用冷冻仲裁器状态接收相等的访问。总线访问时间可以被划分为每个包括N个时钟周期的总线间隔（BI）。可以修改BI和GBF，以保证响应于错误条件或中断而在多个BI上进行平衡访问。

9. 发明授权

US5561820A Bridge for interfacing buses in computer system with a direct memory access controller having dynamically configurable direct memory access channels 失效
标题翻译：用于在计算机系统中与具有可动态配置的直接存储器访问通道的直接存储器访问控制器接口的桥
公开(公告)号：US5561820A
公开(公告)日：1996-10-01
申请号：US351220
申请日：1994-11-30
申请人： Patrick M. Bland , Daniel R. Cronin, III , Richard G. Hofmann , Dennis Moeller , Lance M. Venarchick
发明人： Patrick M. Bland , Daniel R. Cronin, III , Richard G. Hofmann , Dennis Moeller , Lance M. Venarchick
IPC分类号： G06F13/28 , G06F13/40
CPC分类号： G06F13/28 , G06F13/4027
摘要： A bridge interface for buses in a computer system has a direct memory access (DMA) controller that controls memory transfers in the computer system. The DMA controller has a pair of cascaded DMA controller chips that provide a plurality of DMA channels. A multiplexer circuit receives memory address signals from the DMA controller chips. The memory address signals are received in both a shifted form and an unshifted form at the multiplexer inputs. By selection of the shifted or the unshifted memory address at the multiplexer, either even or odd addresses are produced at the multiplexer output for each DMA channel, thereby selectively providing 8-bit or 16-bit memory accesses. The control of the multiplexer is programmable for each DMA channel, providing dynamic configuration of the DHA channels as either 8-bit or 16-bit channels.
摘要翻译：用于计算机系统中总线的桥接口具有控制计算机系统中的存储器传输的直接存储器访问（DMA）控制器。 DMA控制器具有一对提供多个DMA通道的级联DMA控制器芯片。多路复用器电路从DMA控制器芯片接收存储器地址信号。存储器地址信号在多路复用器输入端以移位形式和非移相形式被接收。通过选择多路复用器处的移位或未移位的存储器地址，在多路复用器输出处产生偶数或奇数地址，用于每个DMA通道，由此选择性地提供8位或16位存储器访问。多路复用器的控制可针对每个DMA通道进行编程，提供DHA通道作为8位或16位通道的动态配置。

10. 发明授权

US5450551A System direct memory access (DMA) support logic for PCI based computer system 失效
标题翻译：用于基于PCI的计算机系统的系统直接存储器访问（DMA）支持逻辑
公开(公告)号：US5450551A
公开(公告)日：1995-09-12
申请号：US68477
申请日：1993-05-28
申请人： Nader Amini , Patrick M. Bland , Bechara F. Boury , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Patrick M. Bland , Bechara F. Boury , Richard G. Hofmann , Terence J. Lohman
IPC分类号： G06F13/28 , G06F13/30 , G06F13/36 , G06F13/40 , G06F13/364
CPC分类号： G06F13/4018 , G06F13/30 , G06F13/36
摘要： A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
摘要翻译：提供直接存储器访问（DMA）支持机制用于计算机系统，其包括（i）通过第一系统总线连接到系统存储器的中央处理单元（CPU）和连接到CPU的第二系统总线; （ii）将第二系统总线连接到外围总线的主桥; （iii）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，标准I / O总线具有连接到其上的多个标准I / O设备; 以及（v）以仲裁模式起作用的仲裁逻辑，用于在竞争访问标准I / O总线的多个标准I / O设备之间进行仲裁，并且在授权模式中，授权选择的标准I / O设备被授权访问到标准I / O总线。 DMA支持机制包括代表所选标准I / O设备执行DMA周期的直接存储器访问（DMA）控制器，以及直接存储器访问（DMA）支持逻辑，用于通过外设总线执行DMA周期。 DMA支持逻辑包括直接连接DMA控制器与I / O桥的边带信号，边带信号包括识别DMA控制器正在执行DMA周期的所选I / O设备的总线大小的信息。

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